Prototype Design And Implementation Of Deblocking Filter For MPEG-4 And H.264 Decoder

The block-based encoding method has been widely used in video compression, for it has more advantages than other encoding methods in performance, complexity, compatibility, and market demand. Since the separate quantification of block can bring errors, additional block-based video coding system inevitably encounters the block effect problem. The bigger the quantification step, the more obvious the blocking effect in visual effect and compression efficiency. In order to eliminate blocking effect, MPEG-4 video compression standard introduces a post-processing deblocking filter. It uses various decoding parameters such as quantization step size to smooth the decoded video to eliminate the false edges. The deblocking filter works as a codec module in H.264 video compression standard. It eliminates the accumulation of errors by using the filtered frame as the follow-up motion compensated prediction frame.The main object of this thesis is to design a deblocking filter decoder for MPEG-4 and H.264 decoder. The contributions are summarized as follows.(1) The deblocking filter decoder hardware architecture has been designed. With top-down method, the deblocking filter decoder hardware architecture has been divided into several sub-modules. All sub-modules have been presented in detail, including the function, the hardware architecture and operation timing.(2) The performance of key modules has been optimized. First, the sequence of the deblocking filter has been rearranged, and the filter algorithm has been optimized. Second, the frames have been extended at the upper and left frame boundaries for 8/4 pixels in depth in order to avoid the irregularity of the control unit. At last,a macro-block based double pipelining design technology has been adopted to improve efficiency of data flow control scheme and parallel calculation.(3) The memory architecture has been optimized. An 8-bit dual-port memories with reading and writing simultaneously have been used to optimize the data storage architecture, which effectively reduces hardware cost. The design of data reuse mechanism has been used to reduce the data throughput, effectively saving hardware overhead and increasing filtering speed.(4) The FPGA prototype of deblocking filter decoder has been designed and implemented. The proposed hardware framework has been implemented with Verilog language and simulated with EDA software in RTL simulation and gate-level simulation. The deblocking filter decoder has been integrated into a MPEG-4/H.264 decoder, which has been implemented on FPGA prototype. Experiments with real video streams have showed that the post-processing deblocking filter decoder can meet the real-time decoding requirements of the MPEG-4 simple profile and advanced simple profile, and the H.264 deblocking filter decoder can meet the real-time decoding requirements of the H.264 main profile.