The Analysis And Research Of Boundary Scan Test Technology

In recent years, with the rapid development of electronic technology, the chipsbecome more and more integrated, and package technology is widely used.However, thephysical pins available for testing becomes fewer,conventional probe testing method cannot meet the test requirements of modern complex circuits. It is recognized that the testshould be taken into consideration while the circuit is designed.From the middle of1980s, boundary-scan test method becomes mature and iswidely used in industry, and later forms the IEEE1149.1standard. Boundary scan test isa mothed design for test,it requires only5pins and can achieve data transmissioncapabilities.It can not only test a variety of integrated circuit chip, also can test thecorresponding printed circuit board.Firstly, the author discuss the design for concept of testability,and briefly introducesome common design for test method. Then,detail the structure of the boundary scan testand their testing theory, then, propose the idea that use of the FPGA boundary scan testmethods to test in software test, and is demonstrated, then model and analysis thestructure of the boundary-scan using verilog.Finally, propose the basic theories and methods of the boundary-scan test, anddiscuss the compactness and completeness of the boundary-scan test, and research theoptimization of a set of test vectors generated problems, prove the anti-aliasingTheorem of the test vector set and and carefully analysis True/Compliment algorithmand minimum weight algorithm, and improve on existing algorithms. Meanwhile,propose a complete self adaptable algorithm for diagnosis, base on the W step andoptimize C step diagnostic algorithm,propose new comprehensive diagnostic algorithmand the algorithm improve on compactness and completeness.