On-chip Network Fault Tolerance Design, Testing And Granularity Modeling

As the development of semiconductor technology and the improvement of IC integration, the disadvantages of traditional bus based SoC become much more obvious, and NoC is then proposed and developed. The area and number of transistor of single chip is increasing quickly, at the same time, however, more manufacturing defects and several failure mechanisms in chip operation such as electro-migration, stress migration, time-dependent dielectric breakdown and hot carrier injection will affect chip to obtain satisfactory yield and lifetime reliability. Therefore, fault tolerance of NoC is becoming much more important.After a serial of researching on fault block models of2D-mesh NoCs, this thesis proposes a fault block model which could handle any defect links in bidirectional network and any defect paths in20-path router. It could deal with defect components in arbitrary location, including boundary, corner and internal defects in NoC. It shows from the simulation results that the proposed fault block model could achieve about93.3%available IPs with2%failed links and router paths.With the proposed fault block model, this thesis proposes a partly adaptive fault tolerant routing algorithm which is deadlock freedom, livelock freedom, and it only uses40bits routing info for routing and always try hard to route message with Manhattan path unless countering defects. The results illustrate that, the proposed routing algorithm not only with powerful fault tolerant ability, but also with reconfigurability, expandability, and high throughput.Test is an important process of IC manufacture, especially for the for the fault tolerant design. After a survey of fault models and test method for NoC, This thesis proposes a integrated test circuit which could testing FIFO, crossbar, link and each path of20-path router with much lower area cost. The results show that, the ratio between area of testing circuit and the area of router is becoming smaller when increasing the mesh size of NoC.Performance is one of the most important targets in NoC design, and it is affected by a lot of factors, such as area, yield, application, and lifetime reliability. Based on the performance, yield and lifetime reliability modeling and analysis of NoC, this work proposes a metric directing how to choose the granularity of NoC at high level design in order to obtain high performance when yield and lifetime reliability are considered. The results show that, with the given area (300mm2) and certain applications, the optimal performance is obtained at3x3mesh, and optimal design becomes4x4mesh when yield is considered, and it will prefer5x5mesh or6x6mesh when lifetime reliability is further considered.