| With the development of semiconductor and VLSI technology, integration of transistors on one single chip is constantly increasing. What’s more, processors have entered the muti-core era, the number of cores in one chip is also increasing. Under this circumstance, Network on Chip (NoC) is replacing bus in traditional System on Chip (SoC) as the mainstream interconnection method in Many-Core systems [1]. But at the same time, the high integration and shrinking feature size is accompanied by increasing manufacturing defects and lifetime chip failures caused by electro-migration, stress migration, time-dependent dielectric breakdown and hot carrier injection. What’s more, the developing technology has also brought the problem of severe on chip crosstalk and process variation. These factors will incur runtime fault in the chip. Thus, in order to gain a satisfying yield and reliability, fault tolerance of NoC is becoming an important study field.We developed a fine grained data-path fault model of routers in the NoC. And based on that model we built a 100-core NoC platform with our fault tolerant router and test cores. In the platform, we use BISR[4] to test links and crossbars in the NoC. The results shows that, under realistic link and crossbar fault distribution, the NoC and routing algorithm proposed by this work can reach more than 98% core availability. The NoC proposed in this work considers not only the fault on the chip but also process variation of the links and crossbars. By disabling low frequency links in the NoC, we can increase global clock frequency by 10%, increase throughput by 8.36% and decrease the average transmission latency by 10.42%.After analyzing the shortcomings of the BISR test structure, we proposed a new multi-layer network test access method which enjoys high test input reliability, high parallelism and high efficiency. This structure adds broadcasting network and gathering network on top of the network under test. Taking advantage of data redundancy, this structure and the customized routing algorithm can ensure the reliable input and output of test vectors. And thanks to its parallelism, this structure saves a lot of test time. To give a complete test method of NoC we also proposed some test methods for all components in the router. According to the result, the multi-layer structure in this work saves 56% area and 85.8% of the test time when compared with BISR structure in a 100-core NoC. And due to the complete test method, the test coverage is 100%.Quantitative analysis is very important in guiding the design of processors. It is the same with the many-core processors based on NoC. In this paper we consider not just performance which is usually considered as the most important and only one factor of processor modeling. We also take yield and lifetime reliability into consideration to form an integrated metric in building our model to guide the many-core system granularity decision. First we run SPLASH2 benchmark on simulators to gain performance and area data of the single-core processor. And we use curve fitting to study the relationship between single-core performance and area. By adding programming style and communication pattern we developed our many-core system performance model. We also build up the yield and lifetime reliability model for many-core system. And combing these three factors we build a new metric PYR to evaluate many-core system with different granularities. The results show that, with the given area (300mm2), an 8x8 system will get the best result when considering both performance, yield and lifetime reliability. |
PDF Full Text Request