Design and Development of Reliable and Fault-Tolerant Network-on-Chip Router Architecture

Networks on Chip (NoC) systems have been proposed as potential solutions for the interconnect demands in multi-processor System-on-Chip (MPSoC) environments. With the increase in the number of transistors on-chip and as CMOS technology scales down to nano technology, electronic components and interconnects are vulnerable to the effects of radiation, temperature variations and fabrication defects. The reliability of interconnection networks becomes a critical design factor. This has led to the design and the development of robust and fault-tolerant architectures.;This dissertation addresses some of the key challenges in designing fault-tolerant NoC systems. Fault-tolerant adaptive routing algorithms for 2D mesh NoC architectures are proposed. The new adaptive routing algorithms for NePA architecture are able to tolerate faults in links in the NoC by rerouting packets in a proper alternative direction. The required hardware and software extensions are discussed and the performance of the router design is evaluated. The performance and its hardware complexity of the router demonstrate the feasibility of providing fault-tolerance design for NoC. Moreover, deadlock and livelock situations affect the functionality and the performance of NoC platforms. Thus, this dissertation considers these challenges as well when developing routing algorithms. The routing algorithms are verified to provide low overhead performance while ensuring deadlock/livelock freedom. This dissertation also proposes fault-tolerant routing algorithms for high throughput Diagonal Mesh NePA (DMesh) NoC. The routing algorithms are optimized to achieve efficient performance and low cost overhead while maintaining the correctness and deadlock/livelock freedom.;To achieve high performance computing, hundreds of cores are integrated inside a chip. As cores and interconnections run synchronously at certain frequencies, Electromagnetic Interference (EMI) becomes very high and may affect the electronic circuits and therefore generate faults. An asynchronous NoC chip that is based on delay-insistent logic is proposed. Performance evaluation has demonstrated the proposed approach as a solution to implement Globally Asynchronous/Locally synchronous (GALS) architectures.