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A Research On Multi-granularity Hierarchical Fault Modeling And Simulation For Network-on-Chip

Posted on:2018-07-25Degree:MasterType:Thesis
Country:ChinaCandidate:C WuFull Text:PDF
GTID:2348330512484789Subject:Engineering
Abstract/Summary:PDF Full Text Request
With the development of integrated circuit technology,many drawbacks of SoC based on the bus communication architecture is becoming more and more prominent,NoC architecture comes into being.However,due to the increase in chip integration,NoC chips in the production process and operation are more vulnerable to the impact of process fluctuations,resulting in the increase of failure possibility.Therefore,NoC fault model and fault-tolerant reliability become the research hotspots in recent years,but the fault model of this stage is unreasonable.The fault-tolerant routing algorithm can be improved by the corresponding fault model to ensure the maximum reliability of the system.Based on this,this paper studies how to establish a reasonably applicable fault model and the corresponding fault-tolerant routing algorithm.The main work is as follows:(1)This paper studies the fault model of NoC transport layer,establishes the coarse-grained error packet and fine-grained packet loss fault probability model.The relationship between noise voltage and channel bit error rate in NoC communication is analyzed.Combining the code principle of hamming code and cyclic redundancy check,this paper gets their respective error correction limits.Then the packet structure of this paper is given,and the corresponding coarse-grained error packet and fine-grained packet loss model are given.(2)This paper studies the fault model of NoC link layer,establishes a coarse-grained link delay fault model and fine-grained crosstalk timing violation fault model.For the coarse-grained link delay fault model,this paper firstly analyzes the influence of the process fluctuation on the circuit parameters under the condition of ultra deep submicron,and gives the delay fault model according to the Elmore delay model and the delay margin.For the fine-grained crosstalk sequence fault violation model,the approximate Gaussian distribution of crosstalk time is obtained by using the double exponential crosstalk model.According to the timing constraints of the normal operation of NoC circuit,the crosstalk sequence fault violation model is given.Finally,the rationality of the two models is verified by the experimental data.(3)This paper studies NoC network layer fault model and fault-tolerant routing algorithm,establishes the multi-granularity active link fault models and quantizedmicro-grained node function fault model,and presents a simple and fast fault measurement method,realizes fault-tolerant routing algorithm based on cache dynamic reuse.This paper first defines NoC active link,the establishes different granularity active link fault models.As to some uncertainty of the current functional failure model,a quantitative function model of node function is proposed.By adding the input and output cache switch,to achieve a simple and rapid measurement method.Finally,the fault-tolerant routing algorithm is implemented by dynamically reusing the port cache that is temporarily unavailable and the local idle cache.EsyNet simulation results show that the multi-granularity active link fault model in this paper is more reasonable;Measurement method is small overhead and high speed,with a better comprehensive performance;The CDRRA-QFM algorithm is superior to the current routing algorithms based on functional fault model in both average network latency and through put.
Keywords/Search Tags:network on chip(NoC), hierarchical, multi-granularity failure model, cache dynamic reuse fault tolerance, EsyNet
PDF Full Text Request
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