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Improvement On Endurance Performance Of Embedded Super Flash Memory With Sst 0.25μm Technology

Posted on:2009-05-29Degree:MasterType:Thesis
Country:ChinaCandidate:P YangFull Text:PDF
GTID:2198360242477449Subject:Software engineering
Abstract/Summary:PDF Full Text Request
SST super flash is fast emerging as a mainstream memory technology. Due to high read current and complete immunity from over-erase, SST split-gate flash memory has gained a lot attention in both stand-alone and embedded nonvolatile applications. Flash memory is widely used for many application fields at present such as personal PC, digital machines, mobile telephone, and SIM cards.At the beginning, the paper introduces the flash technology working mechanism and SST 0.25μm process realization method. The split-gate flash memory cells were fabricated by double level polysilicon by using standard 0.25μm CMOS technology. SST split-gate flash memory cells use poly-to-poly FN tunneling for erasing and source side channel hot electron injection for programming.For SST flash, erase failure is the dominant failure mode after cycling due to trap-up in tunneling oxide between floating gate and control gate. The paper focuses on the endurance cycle improvement achievable method discussion. With so many practices and experiment showing, the author achieves the below methods to improve the flash endurance cycle. IP design related: By changing Metal 1 and Metal 3 mask, increase the erase voltage from 12.8V to 13.2V that be cumulated in internal charge pump. 300K sector erase can pass without failure. Process related, by optimizing the recipe on floating gate photo module,adjusting the integrated process recipes on floating gate oxidation formation and the floating gate etch time, changing the tunnel oxide thickness directly to find out the best condition, the erase efficiency is increased obviously.The research was from the company projects and it can be used as reference to other flash product development and production.
Keywords/Search Tags:flash memory, embedded memory, endurance, split-gate, FN tunneling, CHEI, erase, program, reliability
PDF Full Text Request
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