Improvement Of Erasure Performance Of Flash Memory In 70nm Splitting Gate Process

With the popularity of electronic products, flash memory, as today’s mainstream storage carrier spread quickly, and its technology has also been developed rapidly. The split gate flash, which is one kind of the flash memory, due to its highly efficient programming speed and the ability to completely avoid the over-erase, get people more attention both in stand alone and embedded flash. At present, the split gate flash memory has been widely used in personal computers, digital equipment, the mobile terminal, smart cards and other products.This thesis first introduces the fundamental operation mechanism of split gate flash and the formation process in70nm technology. The split gate flash cell use Source-Side Hot Channel Electron injection(SSI) mechanism to program and poly-to-poly Fowler-Nordheim (FN) enhanced tunneling to erase, with the excellent reliability and data retention performance.With the request of high density flash memory in market, the size of the split gate flash memory has kept shrinking. In the period of split gate flash scaling down development, it has the problem of erase inefficiencies and program disturb. Due to there is no intentionally sharpened floating gate tip profile in70nm node split gate flash, without enough forward tunneling voltage from floating gate to erase gate, the electron would be trapped by tunnel oxide, which leads to weak erase. In the program process, although the split gate flash has efficient program performance, the unwanted program cells which share the same bite line or word line with programmed cell applied voltage may be programmed. The reason is the band-to-band tunneling effect in split gate channel produces electron-hole pair, which tunneling to float gate through oxide layer and inducing lower threshold voltage, program disturb occurs. The author of this thesis, through many experiments, proposals how to improve both erase and program performance by structure and process optimized in70nm split gate flash, such as raising the erase speed by reducing floating gate neutral Vt and optimizing floating gate profile at erase gate side, decreasing the program disturb ratio by modification the cell Vt implant integration process. The research technique of this thesis is from the develop experiment in company, and has the reference significance for the similar flash memory product development and manufacturing.