Beyond-One-Cycle Loop Delay CT Sigma Delta Modulators Based On Proper Rational NTF Synthesis

In recent years,rapid development of wireless broad-band communication systems has necessitated the development of power-efficient, higher signal bandwidth and higher dynamic range analog-to-digital converters (ADC). Continuous-time Sigma-Delta modulators(CTSDM) have recently been explored for wideband data conversion due to their low power consumption and inherent anti-alias filtering (AAF), when compared to their discrete-time counterparts.Recently, CTSDM is approaching higher bandwidth applications with high resolution requirements, such as 5G Wi-fi defined in IEEE 802.11ac. This trend implies a higher clock rate of modulators, since the oversampling ratio (OSR) is saturated as low as 10x-20x. A key factor to impede this higher rate trend is the excess loop delay. Most conventional designs allow a loop delay of a half cycle with compensation. Hence, the maximum rate is constrained. This design begins with modifying the noise transfer function (NTF) of CTSDM, in order to obtain a proper rational NTF (PRNTF), thus the maximum tolerable loop delay of the modulator can be extended to twice the clock cycle. After that, successive approximation register (SAR) ADCs can be used as internal quantizers to perform its high power efficiency. Based on this method, this design begins with synthesizing the PRNTF in Matlab and modeling the system in Simulink. The loop filter utilities a 3 order feedforward-feedback (FF-FB) mixed architecture and the influence of various nonidealities on the overall system have been considered, including finite gain-bandwidth product, excess loop delay as well as clock jitter; in succession, Verilog-A modeling in spectre environment, thus specifying more detailed circuit parameters; finally, the implementation of circuit blocks, including design and optimization of opamps, comparators, latches, DACs and clock generators, etc.The modulator is realized by TSMC 0.13um CMOS process. Operating at the clock frequency of 640MHz, the core consumes 27.2mW power dissipation and reaches 80.38dB SNDR under 1,2V power supply.