Research And Design Of High Performance Reconfigurable DWT Accelerator

Due to its multiresolution property and specialty of representation forlocal features of signal between time-frequency, discrete wavelettransform(DWT) is widely used in many fields like signal analysis, datacompression, pattern identification, and computer vision.Despite the fact that lots of researches have been done to optimize theVLSI architecture for specific kind of wavelets, the scalability andgenerality of the circuit were rarely mentioned. Since length of the waveletfilter can be totally different for different applications, the reuse of thecircuit can be a critical requirement. Also, the limited bandwidth andmemory size become obstacles for the practical2-D wavelet system to dealwith different size of input data. In this paper, methods to overcome theseproblems are described and a reconfigurable architecture for DWT withstrong generality is introduced. This architecture can deal with both1-D and2-D DWT with any kind of wavelet functions and different size of inputs.The reconfigurable architecture is mainly based on the convolutionapproach, which has better scalability than the lifting structure. Polyphasemethod is employed in our design to optimize the throughput, and a MACloop based FIR filter is used as the base processing unit to emulate thecomputing process of filters with different lengths. To achieve thegenerality of the system, an innovative data feed strategy and a new taskdivision method is used to guarantee that the requirement of memory size isindependent of the size of input data, such as a picture, in2-D DWT. Theparallelism of the system is enhanced by pipelining and data hazardproblems are eliminated by data unrolling method.The proposed reconfigurable structure was implemented and verified on Xilinx FPGA platform. When dealing with1-D DWT, the speedup ofthe structure is no less than15x compared to Matlab, and for2-D DWTtasks, the speed up is around5x.