Implementation And Application Of Hardware Accelerator Based On Image Recognition Technology

In recent years,the development of convolutional neural networks has reached unprecedented heights.Convolutional Neural Networks can be applied in many fields,such as computer vision,natural language processing,medical equipment and other fields.At present,with the expansion of the application range,the requirements for convolutional neural networks are getting higher and higher,not only in large-scale servers,but also in embedded systems at the edge.The requirements for other conditions are becoming more and more stringent.This thesis designs and implements a hardware accelerator system based on FPGA from the aspects of neural network structure,hardware architecture,performance,power consumption,etc.,and applies it to practical scenarios,and has achieved good research results.The main work contents are as follows:(1)A high-throughput on-and off-chip data transmission scheme is built by rational use of the resources on the board,and a data block and data multiplexing scheme is designed to reduce the delay of on-chip data transmission and ensure the maximum utilization of on-chip data.(2)The computing core of the hardware accelerator is designed,and five different functional layers are designed by using the pipeline design idea,which improves the computing efficiency,improves the utilization rate of DSP resources,and obtains higher computing performance.(3)The activation function and batch standardized structure in the neural network are optimized for hardware design,and the scheme of software and hardware co-design is explored to give full play to the performance of the heterogeneous So C platform used in this thesis.Software and hardware co-design can shorten the design cycle,reduce the design difficulty,and make full use of existing resources to achieve higher performance.(4)Simulation and implementation of the hardware accelerator.Based on the customized hardware accelerator,an accelerator system is designed and built,which can realize the real-time video object detection function.Integrate hardware accelerators with camera,zoom and other modules into an accelerator system for application in practical scenarios.The accelerator system is designed and implemented on the Zynq-ZC706 development platform,the main frequency is 200 MHz,the average actual performance of the YOLO-v2-tiny neural network is 108.78 GOPS,the unit DSP performance ratio reaches 0.2754GOPS/DSP,and the unit power consumption performance ratio The on-chip power consumption of21.613GOPS/W So C is 5.034 W.Compared with the visualization function implemented by the Intel I7 8700 and GTX1080 platforms,the accelerator system has obvious advantages in power consumption,and the recognition frame rate can reach up to 20.7FPS.