Design Of A Dynamically Reconfigurable Residual Network Hardware Accelerator

In recent years,with the development of intelligent hardware and 5G technology,strong real-time applications such as smart security,biomedicine,and automotive electronics began to rise rapidly.At the same time,AI tasks are becoming more and more complex,and neural networks require more and more computing power,which makes it impossible for cloud computing or edge computing to meet the needs of terminal equipment for low latency and strong computing power.In order to solve the above-mentioned AI technology applications For difficult problems,the hardware acceleration of neural networks has important research significance.For terminal hardware,FPGA has the characteristics of low power consumption and high performance,and is more flexible than dedicated ASIC chips,and has a low development cost.It is very suitable for AI application scenarios with frequent algorithm updates.However,most of the current hardware acceleration schemes are statically reconstructed architectures,which cannot dynamically adjust the internal structure and functions according to different needs,and lack hardware support for new structures such as residual neural networks.In response to the above problems,this article is oriented to the application of residual networks,and carries out research on network lightweight schemes and dynamic reconfigurable architectures,and proposes a dynamically reconfigurable residual network hardware acceleration scheme.The main work and innovations of the thesis are as follows:1.Aiming at the difficulty of neural network deployment,this thesis proposes a SupertileINT8 dynamic quantization scheme based on the idea of software and hardware co-design,so that the frequency of the computing unit can reach twice the system's main frequency;using INT8 weight splicing calculation technology to cooperate with compensation.As a result of factor correction,the convolution calculation speed can be increased by 4 times.2.Aiming at the problem that the current hardware accelerators are weak in generality and difficult to adapt to different networks,this thesis proposes a dynamic reconfigurable architecture with hybrid granularity,which can flexibly control the calculation path according to the pre-configured information,and choose among different network acceleration tasks Optimal calculation mode.3.Aiming at the problem of the single support of traditional hardware accelerator operators,this thesis proposes a residual network hardware acceleration scheme,which reduces the calculation delay by storing residual data through additional on-chip cache.Taking the accelerated Res Net-50 as an example,the processing speed of this solution can reach 156.7frames per second,the computing power is about 4.35 times that of ARM devices,and the energy consumption ratio can reach 53.67 GOPS/s/W.Based on the Xilinx xcku060 chip and the Vivado development platform,the thesis completed the system design,functional simulation and performance evaluation of the dynamically reconfigurable residual network hardware accelerator.Through experimental demonstration,the system designed in this thesis has the characteristics of high energy efficiency ratio and strong scalability,which lays the foundation for practical engineering applications.