Design And Research Of Reconfigurable Hardware Accelerator Unit Based On Memory Bus

The design of hardware accelerator has been become the solution of expand science application in universal CPU computing platform.The reconfigurable accelerator not only has flexibility of microprocessor,but also has high performance of application specific integrated circuit.In order to take advange of the excellence of CPU and ASIC,reconfigurable hardware is coupled with a traditional microprocessor.They become hybrid reconfigurable system.In a hybrid reconfigurable system, there are four ways in which these two computation structures may be coupled.Reconfigurable hardware can be coupled as function unit or coprocessor of CPU.Also, they can memory-coupled or IO-coupled. The memory bus has the property of high-bandwidth,low-latency and short communication length,so memory-coupled reconfigurable hardware accelerator unit is suit for computing-intensive applications such as cryphotography and image enhancement.Then this paper puts forward a architecture of memory-coupled reconfigurable hardware accelerator unit(RHAU) and system integration.Task FPGA deals with memory bus protocol,recognises address and incepts the data.The driver changes the register of memory controller after operating system is started up.It maps the address space to system address,so the application can use RHAU normally. This paper puts forward iterative and pipeline implement of AES algorithm.Both byte substitution and inverse byte substitution are implemented in S-box and combinational pipeline.And this paper give the implement of image enhancement in RHAU.In order to obtain the speedup of AES algorithm and image enhancement implemented in RHAU,the paper advances the analytic model of performance evaluation.The evaluation data obtained by changing SIS simulation indicates that RHAU can speed up the AES and image enhancement.