Research On Implement Of DMC Controller With Hardware Accelerator

Model Predictive Control (MPC) was introduced in the late 1970's. It has become an established control technology in the petrochemical industry. The most concern in application is not the form of the model but function. Dynamic Matrix Control (DMC) is a predictive control algorithm based on step response of the object model. This algorithm does not require a priori knowledge of the controlled object, and is suitable for the process whose mathematical model is difficult to be established precisely. It is widely used for the control of slow dynamical systems. However, there are constraints over the state variables with higher dimensions, which results the multi-constraints of the quadratic programming (QP) problem transformed and low on-line computation performance, so the application of DMC algorithm is restricted severely in the fast system.Recently, the interest in introducing DMC into a wider range of applications besides process industry is increasing. In theory, some efficient algorithms for the on-line solution of the DMC optimization problem can be found in many literatures. An alternative is to utilize hardware architectures for parallel computations. This paper aims to achieve the DMC algorithm in hardware and improve the on-line solution speed of DMC by selecting optimization algorithm which is implemented with hardware. The overall scheme is to embed a soft-core processor, Nios II, into a FPGA chip and design co-processors (hardware accelerators) for it. The entire algorithm runs on the NiosⅡCPU, and vector or matrix operations, which more time consuming, are accomplished by parallel computing of hardware accelerator.To improve the on-line computation performance of the DMC algorithm and enlarge its application field, this paper carries out the research from the following aspects, that can compute the QP problem on the order of 700 times faster.(1)QP solution algorithmEventually, constrained DMC can be transformed into a QP problem, so the on-line solution speed of QP affects the computation performance of DMC directly. Firstly, this paper talks about the principle and calculation procedure of both primal-dual algorithm and interior point algorithm. The complexity of program flow and strong coupling be-tween computation steps of primal-dual algorithm is difficult to be implemented by FPGA hardware architectures. Based on these analysis, this paper prefers to the interior point algorithm. By using matrix transformation which converting the higher-order inversion into the low-level inversion, it can compute the QP problem on the order of 25 times faster. Then classify the algorithm for hardware implementation in the next stage.(2)Hardware accelerationIt refers to two parts:custom instructions and custom components. Custom instruc-tions mean adding single precision floating point operations and square root operations, which can make the operation of a single-precision floating-point 10 times or so faster and the QP solution about 6.5 times faster. On the other hand, according to the read and write timing of Avalon bus interface, two schemes are provided:Slave interface and Slave +Master Interface. After simulation test and performance analysis, the latter is chosen as it can reduce the burden of CPU to a greater extent and make the programme about 2 times faster. Then a general architecture, Avalon bus interface module, and logic function modules are designed. The logic function modules contains vector addition/subtraction, vector elements accumulation, the corresponding vector elements product, vector inner product, product of vector and number as well as matrix inversion. Finally, combining the bus interface module and logic function modules for a hardware accelerator, this makes the QP solution about 4.2 times faster.(3)Nios II CPU architectureGenerally, all of the IP cores should be connected with Nios II CPU by Avalon bus and all of the Master Interface connected with Slave Interface exclusively. This makes the complexity of the system increasing greatly. In this paper, the Pipeline Register is added into the Avalon Bus. By using the Pipeline Bridge technology, the maximum frequency of the system is increased from 150MHZ to 250MHZ.Finally, it comes to the hardware and software design of controller. Hardware design includes:to configure Nios II CPU, to design the communication between DE3 FPGA development Board and ICB Board. Software design consists of QP Interior point algo-rithm, DMC algorithm as well as programming of communication protocols. Real-time simulation results of network congestion controller in the xPC-target show that the DMC controller designed in this paper can meet the requirements of real-time and control, demonstrating the feasibility of the proposed method.The measures adopted in this paper can make the QP solution much faster. How-ever, the contribution of the hardware accelerator is relatively little as the accelerator is designed specially for vector operation. So in further research, Catapult C can be used for the hardware implementation of the QP algorithm. The general hardware accelerators structure and the Avalon bus interface module designed in this paper can be adopted to build up the hardware accelerator, using as a co-processor of the NiosⅡCPU. Besides, in order to improve the accuracy of transmission data, hexadecimal floating-point numbers can be transmitted directly instead of turning floating-point numbers into integers and then amplified which may affect the data accuracy.