The Implementation Of High Performance Hardware Accelerator

In the modem digital signal processing, general purpose processor is difficult to meet the requirements of high-speed and real-time processing of data in some 'specific applications with the increasing complexity of the algorithm and the amount of data to be processed. Heterogeneous multi-core system can assign different tasks to different processor cores for parallel processing. It can accelerate task execution and provide a more efficient and flexible processing mechanism to meet the needs of a variety of applications. Hardware accelerator can improve the computing speed of scientific computing for specific applications. Therefore, the architecture of heterogeneous multi-core system integrated with hardware accelerator is proposed. Some multi-core processors accelerate the operation of specific applications by integrating dedicated accelerators, but their flexibility is not high. Reconfigurable technology can make up the deficiencies in performance and flexibility for the general computing and software calculation by applying reconfigurable technology on hardware accelerator. And it proposes a better solution for complex high-speed signal processing.This thesis studies the reconfigurable computing technology, hardware accelerator,and how to integrate the hardware accelerator in heterogeneous multi-core system based on the trend of development. This thesis makes the following contributions:(1) This thesis analyzes the application characteristics for high density computing according to the demand characteristics of application goals, and studies the characteristics of some matrix algorithms which have a high degree of parallelism and can effectively improve the system performance. The matrix algorithm is optimized for the application target and application platform, and the hardware structure of the matrix inversion algorithm is proposed.(2) A reconfigurable high-performance hardware accelerator for heterogeneous multi-core system is designed on the basis of the optimization algorithm and structure.It is mainly used for matrix operations in the field of high density computing. In particular, the hardware accelerator can be efficiently completed single precision floating-point real matrix inversion operations at any 2n order within the 128 order.(3) The experiment and performance analysis of the designed hardware accelerator are carried out based on the Xilinx V6 FPGA. And the integration of the hardware accelerator in the heterogeneous multi-core system is introduced. It is verified that the designed hardware accelerator has high performance.