Expanding Data Aggregate Of Processor Cache Based On FPGA

The 65nm technology has been the most popular technology at digital IC product and most of CPU enterprises have used it for years.With the release of 45nm technology at Intel Corporation, IC product has make a great progress and CPU with two or four computing core has changed our live.Although the 45nm technology and multi-core comes ture, CPU can not be accelerated without limition. It can not improve place and rout technology and can not increase computing core infinitly in IC design. We must get some new approach to accrelerate CPU. Recently, a lot of instituate has been researching the hardware accelerator and reconfigurable logic unit. That is, it will use other hardware electronic to accrelerate if the arithmetic or software be suit to run at hardware when CPU is computing. Reconfigurable logic unit is used to dynamic configure hardware when it is running. Hardware accrelerator which is corporated with CPU must have its own cache and EMS memory unit and cache can determine its efficiency. Different configuring type and different communication type for cache and DDR2-SDRAM can make different outcome. I will give a new method of cache actualizing for the hardware accrelerator. It will be helpful for the reconfigurable logic of CPU. This paper will include below.Configuring cache with FPGA of Xilinx Corporation and it will be used to simulate CPU's cache. The third part of paper will achieve how to make a DDR2-SDRAM controller by FPGA because the DDR2 is a very immportant mechanism for CPU. The fourth part of paper will give a method how to change C language to hardware language, that is, VHDL language. We will use the Laplace equation to validate the hardware accrelerator. The fifth part of paper will synthesize DDR2, cache and Laplace equation achieved by VHDL. Most important, this part will give some new innovation for commutation between DDR2 and cache which will make great impove in efficiency. The sixth part of the paper will give some test data to prove that the hardware accreletor will better than traditional software. The seventh part of paper will summarize the whole paper.This paper will get conclusion as below:1) FPGA will make the hardware accreletor come true if the cache on it can be achieved.2) It will be proved that hardware has better efficiency than software.3) Cache and DDR2 will expand the data aggregate and accrelete the Laplace equation.