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The Research Of Fast-locking PLL Frequency Synthesizer Based On The PFD And CP

Posted on:2013-04-02Degree:MasterType:Thesis
Country:ChinaCandidate:W LiFull Text:PDF
GTID:2248330392456865Subject:Software engineering
Abstract/Summary:PDF Full Text Request
Wireless information technology and microelectronics technology has been highlydeveloped for over a decade and CMOS radio frequency (RF) communication system is alsounder vigorous research. Being a key component of the RF front, the lock-in speed of PLLfrequency synthesizer determines how fast the communication channels can be switched andhow fast the system can be turned on. While in the time-division multiple access systems andfast frequency hopping spread spectrum systems, it pressingly demands for highperformance frequency synthesizer with fast lock-in speed.Based on the project of45MHz-2.4GHz wideband and low-power fast-locking PLLfrequency synthesizer, the article proposes a design of a high-performance, fast-locking PLLfrequency synthesizer of Phase Frequency Detector (PFD) and Charge Pump (CP).This article is divided into three parts. The first part gives a review of the developmentof the Charge Pump PLL frequency synthesizer in and abroad, including its workingprinciples, types and performances. Part two introduces the instructions and designrequirements of PFD and CP. In this part, optimal designs are taken to solve different kindsof non-ideal effect in the circuits of PFD and CP. The last section offers the author’s finaldesign which complies with the requirements of the overall performance of the PFD and CPcircuit.To sum up, the thesis provides an optimal design to the traditional structures of PFDand CP, proposing a continuous full-differential structure of PFD and multi-charge anddischarge low-voltage Cascode structure of CP. The features of this structure lie in its highspeed, low dynamic power consumption as well as the high accuracy, all of which caneffectively reduce the dead-zone effects in the PFD and non-ideal effects in the CP, hence toimprove the PLL locking time. The simulation results of PFD and CP shows that through theoptimal design, the locking speed is highly improved while the locking time is less than8us.
Keywords/Search Tags:PLL, frequency synthesizer, fast-locking, PFD, CP
PDF Full Text Request
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