| Frequency synthesizer output high purity periodic signal can be used as digital system clock or local oscillator signal for radio frequency(RF)transceiver system.With the reduction of complementary metal oxide semiconductor(CMOS)process size,its advantages of high integration,low cost and low power consumption make it possible to achieve high performance RF circuits.The RF circuit represented by LC oscillator occupies a large area cost due to the introduction of passive devices.In order to guarantee the compact design of frequency synthesizers,thanks to the rapid development of machine learning techniques in recent years,in this dissertation,the neural network optimization algorithm of integrated circuit design,as far as possible on the guarantee of the original circuit structure of locking time,loop bandwidth,and linearity features such as optimization,and it does not increase or increase the area of less cost.The main research results are as follows:1.Design of a fast locking phase locked loop based on artificial neural network:the fifth-generation(5G)wireless communication system puts forward higher requirements for data capacity,data transmission rate and access equipment.In order to reduce the switching time between channels(which is also the locking time of PLL circuit),this dissertation first analyzes and compares the common ways to achieve fast locking of charge pump PLL(Phase Lock Loop),and proposes an automatic frequency correction algorithm based on cyclic neural network,which is applied in the rough tuning design of charge pump PLL.Compared with the traditional binary method to find target sub-bands,the recurrent neural network(RNN)algorithm has a coarse tuning time of 3.9μs for voltage-controlled oscillator(VCO)with 32 sub-bands of 5-bit control word.With the increase of the number of sub-bands,the coarse tuning time of RNN algorithm remains unchanged,which has a good application in multi-channel design.Then,in the process of fine tuning,a new charge pump structure is proposed to reduce the loss of power distribution and static power consumption,combined with the subsequent time digital converter and auxiliary circuit,dynamically adjust the loop bandwidth through phase error,so as to reduce the lock time in the process of fine tuning.The simulation results show that the mismatch current of the charge pump is less than 1%,the area of the PLL core is 0.55mm×0.6mm,the unit delay is 7ns by using3-bit TDC,and the fine-tuning time optimization is reduced from 89.6μs to 73.1μs.2.Design of a neural network-based VCO with high linearity and wide tuning range:in order to achieve the coverage of higher output frequency range,introducing a double oscillator and improving the gain of the oscillator are common means.However,there is a compromise between the above design methods and performance parameters such as phase noise.Firstly,this dissertation studies the common ways to improve the linearity of output tuning curve of VCO,and makes a comparative analysis of their advantages and disadvantages.Then on the basis of the existing circuit implementation,a neural network model based on multilayer perceptron is designed and trained for adjusting variable capacitance bias and fitting tuning curve.Then the structure design of the network,the activation function and the selection of the optimizer are analyzed and selected.Finally,the output results of the neural network model are simulated and verified,and a high linearity voltage-controlled oscillator based on the neural network optimization circuit parameters is proposed.After the optimization of multilayer perceptron(MLP)algorithm,the index R~2 for evaluating the linearity of VCO tuning curve was increased from 0.99986 to 0.99989,and the nonlinear coefficient was reduced from 0.335%to 0.254%.3.Design of a constant loop bandwidth phase-locked loop based on artificial neural network:As a hidden parameter,PLL loop bandwidth affects key performance parameters such as phase noise,loop stability and locking time.Meanwhile,after hardware solidification,there is no effective means to accurately adjust the loop bandwidth.Firstly,the distributed bandwidth compensation scheme is analyzed carefully.Then a neural network model based on multilayer perceptron is designed and trained to adjust the bandwidth of PLL.Then,the linearity and bandwidth adjustment coefficient of VCO are taken as a cost function and the weight is assigned.The sample acquisition,structure design and algorithm implementation of the network model are described and analyzed.Finally,the output results of the neural network model are simulated and verified,and a low area consumption constant bandwidth PLL based on multilayer perceptron optimization algorithm is proposed.Simulation results show that the optimized loop bandwidth varies from-2.66 to 3%,and the power consumption is5.206m W,the additional digital area consumption is 43237μm~2,and the frequency variation range is 1.6-2Ghz under the operating voltage of 1.2V at 130nm process. |
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