Research On Several Key Issues Of Design For Reliability Of SoC

With the Very Large Scale Integration (VLSI) coming into Ultra-deepsub-micron era, the System-on-Chip (SoC) process geometries continue toshrink and the integration rapidly ascends. However, approaching the physicallimits results that SoC increases the sensitivity of the various failuremechanisms. As MOS transistor size decreases rapidly and the gate oxidethickness is declined to2nm even thinner, the effect of negative biastemperature instability influences the speed and the parameters of thetransistors seriously that may cause circuit performance worse or result evenfailure. So it can’t be neglected that detection and mitigation circuit of agingshould be design. In addition, the threat of physical stress on the SoC chip ofmissile is self-evident. The chip during the flight is impacted by the varioustypes of stress, and circuit mechanical structural is damaged. Thus, according tothe working environment of missile chip, more and more attentions are paid tostudying the reasonable device and package size.Reliability problems of timing failures caused by the aging, the SoC chipof missile penetration overload and thermodynamic overload have been studied,the main work includes:To begin with, a sensor called SEAOS that can on-line detect soft error andaging is proposed when the device is working under its normal operation, toagainst SEU and the timing violations induced by aging. Based on a BISTstructure--concurrent built-in logic block observer (CBILBO), the hardwareoverhead is well tolerated by the reuse of sequential units before them idling.The experimental results demonstrate that, compared with several classicalstructures by employing0.18μm technology process, SEAOS has a goodcapacity of detection and a lower hardware overhead.Furthermore, An aging-resilient design called TFM-CBILBO to solvetiming violation due to aging is proposed too, which is based on a BISTstructure—concurrent built-in logic block observer reusing the sequentialelements before them idling. According to the varieties of aging levels, bychange the mode, timing violation can be protected effectively after improve the original CBILBO. Results of experience demonstrate under a range of areaoverhead, compared with traditional design, the delay overhead saves40.0%~71.6%.Finally, the chips of missile have been modeled, simulated and analyzedtwice in different varieties by utilizing ANSYS software. The one is thepenetration overload simulation. We select the QFP package type as geometricmodeling, create material models for the different components, impose gravityloads which keep the chip with different angles, and solve and analysis of theresults of the force. Another is Thermodynamic overload simulation. There istwo-dimensional simulation model to observe the situation of the pin and ball inthe thermal cycling under stress and strain. Results of experiments show that thegeometric chip model of missile exploiting QFP package got the less stress thanthe theoretical withstand value under10000g high acceleration. During missileflight, the connections of the pins and the package bear great stress. It isillustrated that due to differences in thermal expansion coefficient, the bendstress below connections of the pins and the solders and the shear stress onsolders of above and below face is great during the cycling of-55℃-150℃.