The Design And Implementation Of Full Frame CCD Image Acquisition System Based On FPGA

With the increasing development of CCD applications, image acquisitiontechnology requirements are getting higher and higher, especially in real-time,complex processing, computational complexity, low power consumption, small size,portability and development costs. This thesis designed an FPGA-based full-frametransfer CCD image acquisition system according to the study requirements and theprinciples of the CCD imaging.There are several new ideas in this thesis:Firstly, the design of the CCD driving circuit and the CCD output signal processingcircuit. KAF-0261produced by Kodak company is adopted in this theis, and the CCDdriving circuit is designed. The control signals produced by FPGA are level shifted bypower MOSFET to drive the CCD device. Furthermore, the+15V and-10V powersignals needed by KAF-0261are obtained by Low-voltage linear regulatorLT3472chip from Linear Technology CO. Ltd. AD9822is choosed in the system to sample andprocess the CCD output signal, and the chip has a power of15MSPS,14bits resolution,correlated double sampling, programmed gain, clamping and easy to control.Secondly, the CCD timing desing and the configure of AD9822using VerilogHDL. The timing requirements of CCD control signals are analyzed in the thesis. Asdifferent CCD devices work in different ways, the timing requirements are alsodifferent. According to KAF-0261chip choosed in this thesis, the timing configureprogramme using Verilog HDL is produced based on the working principle, and it isconfirmed through the simulation.Thirdly, the design of image transmitting interface based on USB bus. Once theimage signal is acquired using KAF-0261, it has to transmit the image data from FPGAchip to the host PC if the image is going to be displayed and stored. In this thesis, theUSB bus is choosen and the firmware programme based on CY7C68013chip isanalyzed.Lastly, the hardware PCB is designed and the driver on the host PC isprogrammed as well as the testing software. And the hardware circuit is debugged then the host PC displayed the image data received from the FPGA chip to test theperformance of the image acquisition system.