Study On FPGA-Based Embeded Frame Grabber

The application of image acquisition and processing technology in many fields such as machine vision and image analysis is very wide. In most circumstances, frame grabber is only responsible for transmitting the image data captured by the front-end cameras to the computer. In other special circumstances, frame grabber must accurately control cameras and synchronize external light source, in order to implement image capturing, pre-processing and image data transmitting. In this way, users can, depending on the various needs, deal with and analyze the sent-back data, so as to achieve certain purposes.According to the image processing needs of the three-dimensional particle image velocimetry system, whichi is a 2^nd project of 985 SCHEME, an embedded image frame grabber, the heart of which is FPGA, is designed and developed. The logic and algorithms are realized by programming the FPGA chip, in order to achieve both the image acquisition in traditional sense and the control of CCD camera and LASER synchronization exposure function. This breaks the traditional synchronized control methods which is simply relied on increased hardware devices, correspondingly simplify the structure of the hardware system and save the total cost. In addition, the image enhancement algorithm is embedded in the system ,the requirements of high-speed acquisition is met using PCI interface, the widely used Camera-Link is adopted as the image input interface, all these methods enhances the versatility, the transmission rate and anti-jamming capabilities of the system, also simplify the connectivity between the image acquisition equipment and the analog camera. The frame grabber, which is capable of embedded processing, camera control and light source synchronization, will make the image acquisition in many areas such as machine vision systems, image velocimetry become more convenient.First the paper not only proves the makeup and the scheme of the image acquisition system but also the feasibility of the system. Then the hardware design is given. The problem of selecting chip is referred when masterminding the architecture of the system. According to the characteristic of the chip, the card's hardware design theory is expatiated in models. The following is the part of the software of the image acquisition card. The every model of the image acquisition system is implemented by programming the FPGA in VHDL and schematic. Based on the requirements of the image acquisition system, the WDM driver is designed by DriverWorks and application program is also given. The IP core is implemented in FPGA at last. And the function of the IP care is hardware embedded graphic arithmetic--image enhance, in which the parameter can be changed. By using the QUARTUS' logic analyzer (SignalTap), the modules for FPGA design is debugged in hardware, and the timing map and the debug results is given.After tested and analyzed, the acquisition card meet the requirements of "three-dimensional particle image velocimetry system" and the planned targets is achieved.