Implementation Of Digital Image Post-Processing Algorithm Based On FPGA

With the popularity of high definition television(HDTV),ultra high definition television(UHDTV)is believed to be the next hot spot.There are some problems in the transition from HDTV to UHDTV.First,most existing video resources remain in low resolution.Secondly,with the transimission bandwidth limited UHD digital video is transmitted in low frame rate,which results in the mismatch between transimission frame rate and display frame rate.Due to the reasons above,effective super resolution(SR)algorithms and frame rate up-conversion(FRUC)algorithms are required to solve these problems.In this thesis,we mainly focus on the implementation of super resolution algorithm and frame rate up-conversion algorithm based on FPGA platform.As to the super resolution,we realize the real-time system which can scale the 2K@25Hz video to 4K@25Hz video based on Xilinx's Kintex7 FPGA.In the first part,the architecture of super resolution algorithm based on local self example is introduced.Specifically,the low frequency band of upsampled image is obtained through bilinear interpolation;then we utilize the searching and matching process to obtain the high frequency band of upsampled image;finally,the upsampled image is reconstructed by combining the low frequency band with high frequency band gained in the above steps.In the second part,the hardware implementation architecture of the super resolution algorithm is proposed to meet the requirement of real-time video scaling.The system mainly includes super resolution core module and parameter configuration module.The super resolution core module divides every image into 16*16 blocks.Each block goes through the recursive scalaed process for three times to get the upsampled image block,which decreases the bandwidth requirement of the system.In order to improve the ability of system's computational parallelism,the design takes pipeline techinique to process data in a row.For the third part,the system's frequency,bandwidth and resource usage are analyzed.According to the analysis,the system can meet the requirement under the minimum frequency of 109.35 MHz and minimum bandwidth requirement of 10368Mbits/s.As to UHD frame rate up-conversion,we complete the software verification of pixel cache module and hardware verification of frame rate upconversion system.First,the function verification of pixel data cache module on Cadence software platform is introduced.Secondly,in order to ensure the integrity of the verification,the ICC tool is used to analyze the code coverage.Different test videos are used to make sure that the code coverage meets the requirement.Thirdly,the result of circuit synthesis shows that the pixel data cache module can reach 300 M frequency clock which meet the design requirement.Then the verification solution is constructed and realized on FPGA platform to ensure the reliability of the verification.UHD sream box,FPGA development board,HDMI delivery daughter card,HDMI receiver daughter card and 4K display device are used to construct the verification platform.At last,this thesis completes the UHD frame rate up-conversion System's hardware verification based on FPGA platform.