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Design And Implementation Of High Speed ​​Serial Data Transmission Based On

Posted on:2017-04-12Degree:MasterType:Thesis
Country:ChinaCandidate:C K WuFull Text:PDF
GTID:2278330485453033Subject:Information and Communication Engineering
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According to the need of different projects, this paper designed two high-speed interfaces. A signal processor has high demands on transmission speed when transmitting data. USB 3.0 interface has been widely used in market, and it has the characteristics of plug-and-play, high-speed transfer, backward compatibility. The Maximum transmission speed can reach 5Gbps. In this context, we use Xilinx’s FPGA as the control center, Micron DDR2 SDRAM as a high speed and mass buffer for data transmission, and USB3.0 system as a data communication with the computer interface to design a kind of high speed data transmission system. The video acquisition card is an essential hardware device for video processing; it also has a high request for data transmission speed. At the foundation of researching and analyzing the existing high-speed data transfer interface technologies, regards PCI Express bus technology as a research object, we designed a high-speed data transmission system which uses PCI Express interface, and developed the device driver and performance test software on the computer.Firstly, the researching background, domestic and abroad development situation, and the related protocol of USB3.0 technology and PCI-E Interface are introduced; then the system chart of transmission circuits were structured. According to the requirements of task of USB 3.0 interface, a high speed buffer based on FIFO inside FPGA and DDR2 SDRAM and GPIF II state machine in Slave FIFO mode are designed, completes the main control program with VHDL language. According to the requirements of task of PCI-E interface, implemented PCI Express interface logic in FPGA, verify the PCI Express memory read, memory write and complete transactions by operating the internal registers through the PIO mode. The design uses DMA mode to transfer data, this paper introduces the design method of DMA engine module and gives an intensive analysis to the DMA write and read operations.The USB 3.0 interface circuit can realize 150MB/S data error-free code transmission after testing. It solves the speed tight bottles of data transmission; the design uses PCI Express x8 link mode and the data transmission speed can reach 1403MB/S after testing, meets the requirement of the data transfer system.
Keywords/Search Tags:FPGA, USB 3.0, DDR2 SDRAM, PCI-E, high-speed data transmission
PDF Full Text Request
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