With The Function Of Digital Correction 12 Successive Approximation Adc Circuit Design

Analog to digital convertor translates analog signals in the real world into digital signals, which makes it possible for processing analog signals in the digital domain. As digital signal has its unique advantages in processing, storage, and transmission, studies of high performance ADC seems necessary and important. Successive approximation register ADC (S AR ADC), a kind of ADC which has8to16bit resolutions and less than5MS/s sample rate, has low power consumptions and low cost, is widely used in some fields such as potable electronic equipments, biomedicine instruments, wireless sensor networks and so on.In this thesis we mainly designed a SAR ADC system with digital calibration function, which works under125KHz sample rate and has12bit resolutions. Our study begins by studying the basic principles of ADC, and then introduces some different kinds of ADCs about their characteristics and parameters used to specify the performance of an ADC. Comparing with some existing structures, the digital to analog convertor (DAC), which is one of the most important modules in SAR ADC system, employs a C-R-C hybrid architecture. The MSB subDAC is5-bit charge scaling, the LSB subDAC is4-bit charge scaling and the middle subDAC is3-bit voltage scaling, giving out a DAC with5+3+4=12bits resolution. Comparing with the C+C+C structure, this DAC brings in only one scaling capacitor which does not have an integer value, and occupies much less area than the topology with only two segments of capacitors arrays. Minimizing the size of unit capacitor will increase the mismatch considerably, so we employed a digital self calibration system to calibrate the mismatch of MSB capacitors. The details of the arithmetic of the self calibration system are introduced in the thesis.The whole SAR ADC system is designed and simulated based on0.18μm1p6m1.8V/3.3V process. High speed and high precision comparator is composed of3pre-amplifiers and a latch, each pre-amplifier employs output offset cancellation. Analog buffer is realized by an OP-amp which is composed of a folded coscode stage and a class AB output stage, which meets the requirements of high gain and driving large capacitor load. Simulation results of the SAR ADC system indicate that it works normally with125KHz sample rates. The measured DNL is0.3LSB. With9.2KHz input signal the SAR ADC system consumes3.1mA RMS current, and FFT spectrum analysis illustrate that SNR=75dB, SFDR=81dB and ENOB=10.6bit. The core area of the layout of the whole ADC circuit is approximately726×580μm2. While the area of the MDAC and CDAC is139×139μm2.