Research And Implementation Of Adaptive Blind Calibration Of Mismatch In Time-Interleaved Analog-to-Digital Converters

Data acquisition instrument,employed as an essential constituent unit in mixed-signal processing system,is the only bridge that connects the real analog world and the virtual digital world as well as the cornerstone of modern signal processing.Along with the increase of the frequency bandwidth and the instantaneous dynamic range for measuring,the requirement of the conversion speed as well as the conversion resolution of the data sampling equipment have to be enhanced as far as possible.Time-interleaved ADC(TIADC)utilizes multiple parallel ADCs that cooperate in a circulatory manner,which can increase the sampling rate by a factor of the number of the interleaved channel,and is considered as the most promising technology to achieve the ADC with ultra-high conversion speed and conversion resolution.However,this architecture is very sensitive to mismatches between the parallel channels,where a small deviation will result in a serious degradation in the overall TIADC's dynamic performance,which greatly limit the applicability of TIADC.The thesis firstly introduces the working principle of TIADC.By modeling each channel ADC as a linear time-invariant system,we develop the continuous-time,discrete-time,and time-varying system models of a TIADC.According to the discrete-time system models,the desired signal can be easily separated from the error signal.In order to eliminate the error signal,the thesis analyses various calibration methods.In these methods,the adaptive blind calibration algorithm is widely concerned by the researchers,because of its various advantages.However,the current adaptive blind calibration algorithm can't be directly applied to high-speed and real-time scenario due to the structure of the algorithm.To make the algorithm compatible for high-speed and real-time scenarios,an efficient and full-parallel adaptive blind calibration method for frequency response mismatch is proposed,where all the filters adopted in the algorithm are realized by using fast FIR algorithm(FFA).In order to reduce the computational complexity,we present a downsampling signed-FxLMS method to estimate the mismatch parameters,which can substantially save the resource consumption and provide low latency.In addition,this chapter proposes an adaptive blind bias calibration alogrithm based the calibration algorithm for frequency response mismatches,which consumes only 3 adders.The bias calibration algorithm can be cascaded with the frequency response calibration algorithm to form a comprehensive calibration algorithm.Finally,the thesis designs the digital calibration circuit of the algorithm for the practical application.We demonstrate the performance and efficiency of the proposed algorithm through the fixed-point number model in Modelsim.In addition,by means of the Vivado IDE,we mapped the hardware circuit to the Xilinx Kintex 7 FPGA,which validates the performance of the digital calibration circuit in the actual device and analyzing the resource consumption.The experimental results show that the calibration circuit can multiply the real-time calibration speed of the calibration algorithm and suppress the mismatch harmonics to near noise with a small amount of hardware resources.