Hours Of Alternating Adc System For Digital Calibration Algorithm And Fpga Implementation

As the progress of modern communication and signal processing technology, the sampling speed of ADCs is increasing. Meanwhile, ADCs should also maintain high precision. However, the decreasing characteristic line width of ICs makes it difficult to achieve high-speed and high-precision simultaneously. Due to the technology restricting single channel ADCs, Time-interleaved ADC with a parallel sampling structure is an alterative. Using uniformly interleaved clock with lower frequency, M-path parallel ADC system can achieve as M times as the single ADC's conversion speed, with the same precision. However, path mismatch such as gain mismatch, offset mismatch and clock mismatch sharply reduce the system dynamic performance. Therefore, calibrating the system output must be necessary..This paper starts with analyzing the source of channel mismatch and corresponding interference to system dynamic performance. After a brief introduction and comparison of existing calibration method, a new channel mismatch calibration algorithm based on adaptive digital signal processing is proposed. LMS algorithm is used for gain and offset joint calibration. Clock calibration is based on a new least channel variance based goal function and mirror frequency signal modulation based signal delay algorithm, when clock mismatch efficient is adjusted by the differential approximation algorithm.MATLAB simulation is performed in the situation of 2-channel, 200MHz, 14bit time-interleaved system with above mismatchs. Also, clock calibration circuits are designed and implemented on a ALTERA STRATIX III series FPGA, using pipeline and folding. The simulation verification and circuit implementation result both show that the proposed scheme can successfully calculate the channel mismatch, and the ENOB of calibrated code is greater than 11 bits.