The Implementation Of FIR Digital Filter Using FPGA

In the modern electrical system, the FIR digital filter is used for many practical applications for its good linear phase character, and it provide an important function in digital signal processing design. In engineering practice, there is always a real-time and flexible requirement for signal processing. However, software and hardware techniques available for implementation are difficult to meet the demand for the two aspects in the same time. Along with the development of PLD device and EDA technology, more and more electrical engineers use FPGA to implement FIR filter, as it not only meet the real-time requirement, but also has some flexibility.In this paper, a method to implement the FIR filter using FPGA is proposed. The work mainly as follow:(1) According to the basic theory of FIR filters, a scheme of hardware implementation is worked out using distributed arithmetic algorithm. As the scale of the LUT in the distributed arithmetic algorithm is so large, the thesis reduces it with the use of multiple coefficient memory banks and offset-binary coding.(2) From the clew of implementing a stratified, modular design, the thesis describes the hardware design of all functional modules and the FIR system with the VHDL and schematic diagram design methods.(3) At last, a sixteen-tapped low-pass FIR filter is taken as an example, and the simulation design carried out using MAX+PLUSII. The result of the simulation is analyzed with the use of MATLAB, and it proved that the function of the design is correct.The result of the simulation indicates that the scale of the design is small, and the sample rate of the FIR filter can reach 8.8MHz. Modifying the LUT can realize the low-pass, high-pass and band-pass FIR filters respectively, and incarnates the flexibility of the design.