Based On The Fpga Fir Digital Filter Design And Realization

In the modern electrical system, the FIR digital filter is used for many practical applications for its good linear phase character, and it provide an important function in digital signal processing design. In engineering practice, there are often real-time and flexible requirements for signal processing .However, software and hardware techniques available for implementation are difficult to meet the demand for the two aspects in the same time. Along with the development of PLD device and EDA technology, more and more electrical engineers use FPGA to implement FIR filter, as it not only meet the real-time requirement, but also has some flexibility.In this paper, a method to implement the FIR filter using FPGA is proposed. The work is mainly as follows:1. According to the basic theory of FIR filters, a scheme of hardware implementation is worked out using distributed arithmetic algorithm. As the scale of the LUT in the distributed arithmetic algorithm is so large, the thesis reduces it with the use of multiple coefficient memory banks and the symmetry characteristic of linear FIR filter.2. According to the characteristics of hardware realization based on FPGA,the parallel and serial scheme are implemented separately in the paper , using the examples of sixteen-tapped lowpass FIR filter with method of eight-tapped cascade and eight-tapped lowpass FIR filter for each, and also the performances of each scheme are compared through the concrete design. From the clew of implementing a stratified, modular design, the thesis describes the hardware design of all functional modules and the FIR system with the VHDL design methods.3.The design is adopted to the Xilinx Virtex-II serials FPGA, synthesized and simulated with the ISE6.1i. In order to make the verification more available, the complex simulation with Matlab and VHDL is used to testify the design whether fulfills the requirement. And also the result of the simulation is analyzed with the use of MATLAB, and it proved that the function of the design is correct.The simulation results indicate that the scale of the design is small, which proves that the improvement on DA arithmetic is effective. And the highest system clock can reach 100MHz after the improvement. The design indicates the flexibility at realizing the low-pass, high-pass and band-pass filter easily just through some modifications on FIR filters LUT respectively.