Research On The Implementation Of Digital Down Conversion With FPGA

Software radio is one of the hotspots in radio communication and military research. Due to the poor processing speed of A/D/A conversion and DSP processor, software radio often adopts inter-specific schemes based on digital conversion technology. That is to say, by using specific DDC and DUC or running relevant algorithm, software radio transforms the sampling rate to enable DSP processors bring real-time signal processing to success.A Digital Down Converter(DDC) converts an intermediate frequency(IF) band signal into a baseband signal by using a mixer in the digital region and a low-pass decimation filter which can extract one signal channel from the received after the analog-to-digital conversion. Because software radio is broad-band, open, and programmable, it requires high resolution Numerical Controlled Local Oscillator which allows carrier channels to be selected from a wide frequency band, and ,it requires high efficient programmable decimation filters with good anti-aliasing feature which can extract both desired narrow band and wideband signals, it also requires programmable Finite Impulse Response(FIR) filters to reject the out of band signal. Field Programmable Gate Array (FPGA) has efficient algorithm structure and reconfigurable feature, which can support the digital IF processing well.In this thesis, signal processing of DDC is investigated, and the implementation of some key components in DDC is focused on. In the first place, the thesis presents the theory of IF signal processing based on a generic software radio configuration and the mechanism in DDC. Then an Numerical Controlled Oscillator using ROM Look-Up-Table(LUT) technology was designed, which has flexibility and high resolution. Since efficient decimation filters is very important for DDC, Cascaded Integrator Comb(CIC) Filter is concerned. CIC filter has simple structure without coefficients, it carries filtering through delay units and adders, which is suitable for FPGA implementation. In the thesis, a CIC filter with programmable decimation rate was designed. In the blocks of efficient filters of DDC, FIR plays a key role inrejecting the unwanted signals. Distributed Arithmetic(DA) as an important technology has been proved efficient in implementing Multiply-Accumulator(MAC). In this thesis, ROM decomposition technology, offset-binary coding technology and symmetric architecture were used to improve the Serial Distributed Arithmetic FIR structure by ROM size reduction.