Design And Implement Of Non-recursive Digital Filter (FIR)

In the modern electrical system, the FIR digital filter is used for many practical applications for its good linear phase character, and it provides an important function in DSP design. In engineering practice, there are often real-time and flexible requirements for signal processing. However, software and hardware techniques are difficult to meet the demand for the two aspects in the same time. It is facing four challenges: speed, design size, power consumption and development cycle. Along with the development of PLD device and EDA technology, more and more electrical engineers use FPGA to implement FIR filter, as it not only meets the real-time requirement, but also has some flexibility. FIR digital filter has been widely used, so scholars and engineers have been paying more attention to its optimal design.In the paper, a method to perform the FIR filter based on FPGA is proposed. The work is mainly included:(1)Study the Distributed Arithmetic (DA), research the design of FIR digital filter and analyze its shortcomings. In this paper, a set of high-efficient multipliers for FIR, based on CSD coding, is presented, in which various optimized technique for digital filter is used. It has triple value. Application of CSD coding can reduce the number of non-zero elements, in addition, reduce the time of operations, improve the speed and reduce the areas. Its character can be widely used in many disciplines. It is being used in areas such as combinatorial optimization, machine learning and so on. Although the CSD coding has been raised 10 years ago, it is generally used in digital areas, and not really in the design of hardware. This article will attempt to use it to the FIR digital filter design and reflect its coding optimization and the benefits of the hardware design. The experimental results show that CSD arithmetic improves the performance of multiplication, and reduces the use of resources.(2)Design the FIR by using hardware description language and top-down method .One improvement is realized in the design of the multiplication module to reduce overflow errors. Designed a hardware circuit of FIR filter: the main IC is FIR, including A/D convert circuit, D/Aconvert circuit and the system configurable circuit. Use the voice as the input signal, check the actual effect.The experiment prove that this system is real-time, veracity, agile and paracticability comparing with the traditional filter.(3)FIR reconfigurable design.A reconfigurable FIR was designed. Users can get the logic design through it only with initial configuration file, without knowing the machanism of CSD coding.(4)As for IP configuration deficiency, a solution is put forward and a common C language package is designed to resolve the problem.