1.5 Mhz Operating Frequency Radio Signal Phase Lock And Phase Demodulation Technology Research

ADF receiver is one of the first generation of aircraft navigation equipment. ADFkey technology is the PLL and demodulation. The technology of ADF has beencontrolled by foreign countries, which restricts the development of domestic ADF. Inthis thesis, this problem could be solved by only Altera’s FPGA chip (EP3C12~0F780I7).In the digital phase-locked system of this thesis, ADF IF signal digitalphase-locked is completed and the lock-in time is modified through automatically modealteration module. This module coordinates the contradictions among mode value,ripple, and the lock-in time. The maximum locked time is not more than1.8ms. Firstly,ADPLL, performance and parameter settings are analyzed. Based on the analysis,simulation software is adopted to ensure the correctness of the design. Secondly, thecircuits are implemented using Verilog HDL. This system is composed of the digitalphase module, the K-mode reversible counting module, phase control module, Ncounter module as well as automatically mode alteration module. After that, test-casesand simulation testing of each module were programmed. Finally, together with atop-level file and test code, the overall ADPLL system simulation was finished.In the demodulation system, the digital demodulation of the azimuth angle wasachieved, and a new ADF frequency offset detection circuit was designed, including aphase detection module and a FIR filter module. These modules are based on theRTL-level design, and generate circuits which could be flashed in FPGA after synthesis.These modules are tested under ModelSim simulation environmental, the results areverified to meet the requirements.Finally, The digital phase-locked system and position demodulation system hadbeen integrated into an overall circuit. The circuit can be tested in ModelSimenvironment. The test results show that lock time is not greater than1.8ms, the positionerror is less than0.72degrees. It is in full compliance with the main requirements inSJT10127-91, in which the specification is not greater than4s of lock time and lessthan3degrees of position error.