Digital Phase-locked Detection System Based On FPGA

With the continuous development of science and technology, the application of modern signal processing techniques proposed a higher requirement for detection of weak signal. How to detect the weak signal from the noise and obtain the right data is a very important issue.Comparing to other ways, the phase-locked detection is a more effective way for the sinusoidal signal. In this paper, the following works have been done based on the weak signal detection theory and lock detection algorithm:The weak signal detection generally requires the highest resolution,while the over-sampling technology can improve the effective resolution of weak signal detection under certain conditions, and the oversampling technique was combed. The simulation and experimental results show that while the sampling rate increases by 4 times, the SNR can be improved by 6 dB, which means the ADC increases 1 bit.For the classic digital lock detection, due to a lot of multiplication, the calculation speed is low. A new fast-speed digital lock detection algorithm was proposed in this paper. The fast algorithm is as follows: four samples are taken per period from the frequency signal testing required, the orthogonal reference signal values are set to be 0,-1 and 1 to remove all the multiplication and parts of addition, which can greatly reduce the computation. Simulation and actual experiment results showed the calculation for the sampling data of cycles N can be reduced multiplications by 8N times and additions by 4N times. In order to improve the accuracy of the fast algorithm,the fast algorithm based on the oversampling was proposed. The algorithm which takes the advantages of oversampling and fast algorithm used the average down-sampling technology to reduce the sampling frequency to 4 times of the frequency of the original signal. The modification factor was introduced to improve the calculation accuracy of the amplitude,by which the error can be eliminated completely in theory. The results of the simulation and actual experiment showed that the new fast-speed algorithm based on oversampling was valid not only with the high precision of oversampling and lock-in detection,but also with a high speed.Today, microcontroller or DSP is often used as the main controlling chip, but the running speed of the microcontroller is not high, which always become a bottleneck on the data channel, so that the analog-digital conversion chips can not play their best performance;Although DSP chips can run faster, but its price and feasibility is worse than FPGA. The subject used the XC5ULX110T of Virtex-5 FPGA family to control the AD8802 of the digital-analog conversion chip,AD7760 of the analog-digital conversion chip and UART16550 IP nuclear to realize the new digital lock algorithm of a high-speed acquisition.