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The Design And Implementation Of Adaptive Voltage Regulation Circuit

Posted on:2013-12-12Degree:MasterType:Thesis
Country:ChinaCandidate:Q XieFull Text:PDF
GTID:2248330374485889Subject:Microelectronics and solid-state electronics
Abstract/Summary:PDF Full Text Request
IC power consumption is becoming more and more important with the development of portable electronic products and its size trend. Adaptive voltage scaling (Adaptive Voltage Scaling, AVS) is an effective power management technology in recent years. AVS adjust the frequency according to the strategy by monitoring the hardware, and adjust voltage based on the work load. It can reduce power consumption of load by30-70%. The feature of this technology that it can reduce system power consumption but not affect the function of the system and performance parameters at the same time.This paper introduces the concepts and principles of IC power consumption at first, and then pointed out that most effectively way to reduce the dynamic power is reduce the power supply voltage VDD. In these low power management technology, DPM get the balance between system performance and power consumption by turning off the equipment; DVS adjust the voltage and frequency by lookup table belongs to the open-loop regulation; AVS monitor the work load in real time belongs to closed-loop regulation. This paper designs an adaptive voltage regulator circuit based on the delay line load, using top-down methodology, in the0.13um CMOS process. This paper focuses on the AVS logic control module, hybrid simulation and all-digital phase-locked loop module.The critical path of the load and the delay line detection circuit are be focused in this paper. AVSCON is the most important module of the adaptive voltage regulator system and it is the central part to determine the voltage is too large or too small, determines the ability to regulate and adjust the accuracy of the power system directly. Chapter4details the design and simulation of all-digital phase-locked loop, design an all-digital phase-locked loop with TDC structure. Finally, the simulation results and layout based on all-digital process of whole circuit are given.In the last chapter, evaluation of this system is carried out. The author’s work is summarized and deficiencies of this work are presented.
Keywords/Search Tags:Adaptive Voltage Scaling, Load Delay Line, ADPLL
PDF Full Text Request
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