FPGA Anti-degradation Approach Research Using Adaptive Voltage Scaling

Field Programmable Gate Array(FPGA)is a widely used new high-performance logic device in today's hardware design.FPGA has the advantages of powerful,short development cycle,reprogrammable and providing intelligent development tools.However,as the processing technology of Very Large Scale Integration Circuit has gradually reached the physical limit,FPGA devices are facing increasing reliability problems.Among the numerous reliability issues,Negative Bias Temperature Instability(NBTI)is the primary reason of FPGA device failure,and the performance degradation caused by the NBTI effect causes the FPGA to generate more delay.During the transmission time,the signal in the logic gate is gradually extended and eventually lead to circuit timing violations.This paper first analyzes the internal structure of FPGA and the essential reason of FPGA performance degradation caused by NBTI effect,and simulates the LUT structure and interconnection structure of FPGA.Based on this,this paper designs the FPGA experiment platform to accelerate the degradation of FPGA.Using the method based on the failure of physics,we make the FPGA accelerated degradation test,and measure the degradation of FPGA in different stress combinations of the situation under the test.Then the effect of power supply voltage on path delay is studied,and the influence of power supply voltage on the LUT structu re and the delay time of interconnection structure is simulated by HSPICE simulation tool.Besides,the path delay measurement method based on ring oscillator is used to verify the influence of power supply voltage on path delay by real hardware experiment in FPGA.Based on the previous research,this paper presents the basic framework of FPGA anti-degradation method based on adaptive voltage scaling and designs the degradation sensor to monitor the degradation of FPGA path in real time,and adjusts the power supply voltage dynamically according to the degradation condition,to guarantee the circuit performance,and reduce the power consumption of the circuit.Finally,this paper builds a complete realization and verification platform based on the adaptive voltage scaling.The experimental results show that the proposed method can effectively eliminate the influence of FPGA degradation,and it has the advantages of strong robustness and fast response.It can also reduce the power consumption by 57.98% in the same performance compared with the traditional method.In the case of the same power consumption,the method can improve the performance of up to 14.78%.