The Design Of An Adaptive Voltage Scaling Circuits Based On Dominate-pole Compensation

As the integrated circuits technology developed fast in the last few years, more and more functions can be integrated into the same chip area, thus the power waste issue becomes serious. As to IC designers, it is impendency to develop low power ICs.At the other hand, the mobile device such as smart phones and flat computers are becoming smarter and smaller because of the development of IC, while the development of battery lags behind it.Fortunately, life span of the battery can be extended with the employment of low power design.Among all the low power designs, Adaptive Voltage Scaling(AVS)gets more and more attention, because it can sharply reduce total energy.In this thesis, a dominate-pole-based AVS is proposed after analysising several different power management technologies. A low frequency pole which is produced by a backward-forward counter in the loop makes the system stable. The output of the counter controls a Digital Pulse Width Modulator(DPWM), and thus the output voltage can be scaled. The high efficiency Buck converter which serves as it’s power stage works under synchronous rectification.In this thesis, a high linearity DPWM is proposed and designed. It is based on delayline-counter structure. The delayline is calibrated by a novel method that changes the order of calibrating each delayline stage, and thus the Integral nonlinearity(INL)is improved to a great degree.This AVS is a mixed circuit. Through the mixed-signal design and verification methods, we can say that the circuit works correctly, and the voltage can be scaled according to the frequency. The input voltage is 2.7V-4.2V, and the output voltage is0.9V-2.2V. And finally, this circuit is taped out in 0.18?m standard CMOS process.The whole area of this chip is 1300?m×1150?m.After simulation, we can get that this AVS circuit can save as much as 46% energy than DVS.