Adaptive Voltage Scaling System Design For Neural Network Acceleraters

With the rapid development of artificial intelligence,people's demand for neural network accelerator is higher.Therefore,high requirements are raised for power and performance of neural network chip.As with traditional digital circuits,worst-case should be considered in the neural network chip design due to process,voltage and temperature(PVT)variations.Sufficient timing margin should be reserved to ensure the correct function,especially in the near-threshold region.However,the worst-case scenario is less likely to occur,which leads to a waste of power and performance.In order to restrain the impact of PVT deviations and eliminate the reserved timing margin in the neural network,the resilient design represented by adaptive voltage scaling(AVS)can make the neural network work properly in a wide voltage range.It further reduces power consumption and improve energy efficiency over the baseline design with reserved timing margin.However,there are several problems in the existing research of neural network and AVS design:(1)The area and power consumption of transition detector is relatively high;(2)The monitoring point selection is short of evidence while the monitoring cost is large;(3)Approximate calculation is used to modify processing elements(PE)with timing violations,which reduces the accuracy of neural network;(4)The fully-customized layout technology such as body swapping is highly complex in implementation.Thus,a set of in-situ monitoring method and AVS technology for neural network accelerator is proposed in this thesis,which further explores the theory of ‘negative timing margin' based on the complete elimination of timing margin and achieves large optimization of power consumption over the baseline design.In this thesis,a wide voltage and low power transition detector with quick response is designed to monitor the timing of neural network,which is transferred to the upper-level power module to adjust the chip voltage in real time.Then,the path characteristics of the selfaccumulation neural network are analyzed.We present a method of selecting monitoring points in the neural network based on data correlation,in which only one monitoring point needs to be inserted into each PE,reducing the monitoring cost at least 87.5% compared with the published designs.Finally,the theory of ‘negative timing margin' is put forward for neural network,which reduces the timing margin to a negative value on the basis of completely eliminating margins and further obtains lower voltage and higher power savings.The above technology is applied into Keyword Spotting neural network with TSMC 28 nm process.Simulation results show that the proposed scheme of in-situ monitoring and AVS achieves 27.01%?70.45% power gains at 0.32V?0.9V,which has no impact on the recognition accuracy of neural network.For the whole AVS system,the insertion rate of the transition detector is 2.1%,the replacement rate of the latch is 14.8%,and the area overhead of the AVS system is only 1.31%.In addition,the chip performance is 0.22?6 times over the worst-case baseline design.