An Adaptive Voltage Scaling Regulator With Minimum Energy Point Tracking For Digital Load

With the rapid development of integrated circuit technology, Critical Dimension of semiconductor technology has decreased year by year. The 16/14 nm technology is mature and the chip has been in mass production. The 10 nm technology is going to be broken through. Low Critical Dimension and high integration of the chip make power consumption density increasing sharply, which will lead to problems such as heat dissipation, stability etc. At the same time, digital products have been downsized to be portable, which limit the battery’s power supply capacity. As a result, the energy consumption of the digital circuit directly determines the life time of digital products. Therefore, the research of low energy power management technology to reduce energy consumption of digital circuits has become an important topic.This thesis focuses on reducing the digital load’s energy consumption, which proposes a new power management strategy called adaptive voltage scaling with minimum energy point tracking for digital load. The adaptive voltage scaling(AVS) technology and the minimum energy point tracking(MEPT) technology have been introduced and their energy saving characteristics have been analyzed. Based on PSM(Pulse Skipping Mode) Buck DC-DC converter, MEPT technology is combined with AVS technology and an AVS regulator with MEPT for digital load is designed. The circuit is based on critical path replica, which using delay line detection to reflect the load current and working condition of load, and adaptively adjusts the power converter voltage to meet the demand of digital load. The minimum energy point of digital circuit is going to be tracked after the AVS regulator finishing voltage scaling. The output voltage of Buck converter is going to be scaled to the corresponding voltage of minimum energy point, so that the energy dissipation of digital circuit is minimum.Aimed at the proposed AVS and MEPT regulator, the method of combining AVS and MEPT as well as the switch logic between them are analyzed firstly. The framework of the whole system and its working principle are introduced. Then the specific circuits of the critical module in the whole system and the simulation results are introduced in detail. Finally, the circuit design of whole system and the layout design are displayed. Chip package form is assured and the test results are given.The AVS regulator with MEPT for digital load is designed in this thesis with input voltage ranging from 2.7V to 4.2V, output voltage ranging from 0.2V to 1V, operating frequency of digital load ranging from 68 k Hz to 70 MHz. The dynamic energy consumption is saved up to 91%. The energy consumption of digital load is minimized further by combining AVS and MEPT techniques.