Low-power Microcontroller Based On Dynamic Power Management And Adaptive Voltage Scaling

With the rapid development of microcontroller-based products such as Internet of Things equipment and Personal Terminal Equipment.The problems of battery life and heat dissipation caused by power consumption have become more serious,and the chip power consumption accounts for a large proportion.Therefore,the device's battery life and user experience can be significantly improved by optimizing chip power consumption to reduce load energy consumption through Dynamic Power Management(DPM)technology,Dynamic Voltage and Frequency Scaling(DVFS)technology,and Adaptive Voltage Scaling(AVS)technology.The thesis designs and implements a microcontroller based on multi-solutions joint energy-saving optimization strategy.The system power architecture is designed through DPM technology,and a power architecture suitable for low-power microcontrollers is designed and implemented by supporting dual power supplies and multiple working modes.Based on this architecture,some of the power domains are quickly adjusted by DVFS voltage regulation,and then AVS technology is used to further reduce timing margins and optimize power consumption.At the same time,in the AVS circuit,the delay time of the entire delay circuit in the replication critical path is increased by using the delay unit of the double stacked structure.And in order to improve the problem of a large number of different replication critical paths,a method of multiplexing the replication critical paths through a variable boundary is proposed and implemented,and the unknown actual critical path length is tracked by this method.The thesis uses the SMIC 55 nm CMOS process technology to design and implement the power supply architecture and the power optimization circuits.In the design of the power mode,there are many different ways such as NORMAL state,LP?RUN state and AON state.At the same time,according to the actual test results of the chip,when running the core and peripheral functions in the LP?RUN state,the power consumption is only 1% to 10% of NORMAL state,And the power consumption of the AON state is only 0.4% of the LP?RUN state.When the design scheme of combined voltage regulation using DVFS technology and AVS technology is used for the main power domain,the obtained actual power optimization can reduce the power consumption of the main power domain by 12.4% to 58.3%.