SOI Lateral High Voltage Device And Its Breakdown Voltage Model Based On The Enhanced Dielectric Electric Field Principle

SOI HVIC(High Voltage Integrated Circuit) is widely applied due to the advantages such as high speed, low power dissipation, perfect irradiation hardness and superior isolation. SOI lateral high voltage devices are the key devices in SOI HVIC, of which the low vertical breakdown voltage limits the application in high voltage and power integrated circuit. A lot of novel structures have been proposed to enhance the vertical breakdown voltage of SOI lateral high voltage device. However, up to now, silicon dioxide is used as the buried layer and the breakdown voltage of the applied SOI devices is less than 600V. At the same time, as for the analytical models for the electric field distribution and breakdown voltage of SOI lateral devices, the existing analytical models are presented only for SOI device with the constant thickness buried oxide layer and the constant thickness drift region. Furthermore, no unified principle can be used to design SOI lateral high voltage device to enhance the vertical breakdown voltage.In this thesis, addressed the breakdown voltage problem of SOI lateral high voltage device, the breakdown theory, the new device structures and breakdown analytical models are researched. Based on the concept of the critical field approaching for the dielectric field, ENDIF(ENhanced Dielectric layer Field) principle is presented, by which three kinds of the novel SOI lateral high voltage device structures are proposed. The analytical models are presented and some experiment results are obtained for these novel device.1. The vertical breakdown mechanisms of the typical SOI lateral high voltage devices are unified by ENDIF principle.The concept of ENDIF principle is that the vertical breakdown voltage is improved by enhancing the electric field in the buried layer. Three methods for enhancing the electric field in the buried layer are given, including using the low k dielectric buried layer, using thin SOI film and implementing the charges on the interface between SOI layer and buried layer. The expressions for the electric field in the buried layer and the breakdown voltage are obtained under the one-dimension approximation. The vertical breakdown mechanisms for the existing typical SOI lateral high voltage devices are unified by ENDIF. ENDIF principle breaks through the theoretic limit of the vertical breakdown voltage for the conventional SOI lateral devices. It is a general principle to design the vertical breakdown voltage for SOI lateral high voltage devices.2. Based on the ENDIF principle, the following three kinds of novel structures are proposed, for which theories and experiments are carried out..(1) The novel structure and its breakdown analytical model for SOI high voltage device with low k dielectric buried layer are proposed.The kind of the high voltage device includes SOI device with the low-k dielectric buried layer, SOI device with the variable-k dielectric buried layer and Partial SOI device with the low-k dielectric buried layer, in which the low-k dielectric with the high critical electric field is firstly used as the buried layer or partial buried layer. The electric field in the buried layer is enhanced and the ones in SOI layer and buried layer are modulated by the low-k and variable-k buried layer, resulting in the enhancement of the breakdown voltage. By solving 2-D Poisson equation, taking into consideration the modulation effects, the breakdown analytical model for SOI device with the variable-k dielectric buried layer is presented, from which the RESURF criterion is derived. The model and RESURF criterion can also been applied to SOI devices with the variable-thickness buried layer and with the uniform dielectric buried layer. Therefore, the model is a unified model for SOI devices with the variable dielectric buried layer (including the variable-k and variable-thickness dielectric buried layer) and with the uniform dielectric buried layer. The dependences of the electric field distributions and the breakdown voltage on the structure parameters are discussed by the analytical model and the numerical simulation. The results show the electric field of the buried layer and breakdown voltage for SOI device with the variable-k dielectric buried layer are enhanced by 100% and 83% compared with those of the conventional SOI, respectively. For SOI device with the variable-k dielectric buried layer, of which Si₃N₄ instead of SiO₂ is the buried layer at source side, the electric field in the buried layer and breakdown voltage are enhanced by 73% and 58%, respectively, moreover, the maximal temperature is lowered 51%. The analytical results are in good agreement with those of numerical simulations.(2) The novel structures of SOI high voltage device with charge mode and their experimental results are reported. In this thesis, the proposed SOI high voltage device structures with charge mode include (a)SOI high voltage device with the double-side charge trench and PSOI device with the charge trench, in which the dielectric trenches are formed on one or two interfaces of buried oxide layer. The charges located in the trenches increase the electric field in buried layer and modulate the electric field in SOI layer, therefore, the breakdown voltage is enhanced. PSOI device with the charge trench can not only enhance the breakdown voltage, but also lower the self-heating effect; (b)SOI device with the composite buried layer, in which the composite buried layer is made of two oxide layers and polysilicon between them. Its breakdown voltage is shared by two layers buried oxide, furthermore, the charges on the bottom interface of the polysilicon layer enhance the electric field in the second buried layer, so breakdown voltage is enhanced. The fabrication process of SOI material with non-planar buried layer is developed based on SDB(Silicon Direct Bonding) technology. 730V SOI LDMOS with the double-side charge trench and 760V SOI device with the composite buried layer are obtained for the first time. The electric field in the buried oxide layer increases from below 120V/μm of the conventional SOI to over 300V/μm for the former and over 400V/μm for the second buried layer for the latter.(3) The new structure and its analytical model for the thin film SOI high voltage device with step drift region are proposed.The new structure and its breakdown voltage analytical model are proposed. The new electric field peaks are generated at the steps, which modulates the electric field in SOI layer and enhances that of the buried layer, resulting in the enhancement of the breakdown voltage. A breakdown analytical model for the proposed SOI high voltage device is proposed by solving Poisson equation. The effects of the device structure parameters on the electric field distributions and the breakdown voltage are discussed by the analytical model and the numerical simulation. The results show the breakdown voltage for the thin film SOI device with two steps is as high as twice of the conventional SOI device at t_I=3μm , t_S=0.5μm , maintaining the low specificon-resistance. Numerical simulations support the analytical model.