Model And Novel Structures For High Voltage And Low On-resistance SOI Device

SOI （Silicon On Insulator） technology has been widely used in SPIC （Smart PowerIntegrated Circuit） because of its a series of advantages, such as low power dissipation,high speed and high integration density. As a basic component in Smart PowerIntegrated Circuit, the study of high voltage SOI LDMOS （lateral double-diffusedMOSFET） is mainly focused on improving the breakdown voltage （BV） and loweringthe specific on-resistance （Ron,sp） nowadays. It has been proved that the vertical BV canbe effectively enhanced by the low permittivity material in the dielectric buried layer.However, for the drift region above the variable permittivity dielectric buried layer inthe off-state, the formulas of the continuous potential distribution and continuouselectric field distribution are derived only at the surface from the existing analyticalmodel. On the other hand, the drift region with a certain length is needed in high voltageSOI LDMOS to meet its requirement of breakdown voltage, which limits the reductionin Ron,sp. In the study of easing the contradictory between BV and Ron,sp, trenchtechnology is increasingly being used in the design of the device structures. By formingthe dielectric trench filled with SiO₂in the drift region with the usage of trenchtechnology, the trench high voltage SOI LDMOS could obtain the desired BV with ashorter device length, therefore reducing the Ron,spand the chip area needed by thedevice. But, there are few studies on the further reduction in the Ron,spof trench highvoltage SOI LDMOS.In order to ease the contradictory between BV and Ron,spfor high voltage SOILDMOS, this dissertation focuses on the following two aspects: increasing the BV ofhigh voltage SOI LDMOS by using the variable dielectric buried layer and reducing theRon,spof trench high voltage SOI LDMOS. A potential well analytical model for highvoltage SOI device and two kinds of novel structures are proposed. The majorinnovations of this dissertation are as follows:First, a potential well analytical model for high voltage SOI device is presented.Based on the2-D Poisson’s equation, the potential well analytical model for highvoltage SOI device considering the interface accumulated holes is established bymodifying the potential distribution formula. For the high voltage SOI device in theoff-state, the formulas of the potential and the electric field continuous distribution in the drift region above the composite permittivity dielectric buried layer are obtainedwith the established potential well analytical model, and the influences of the differentpermittivity in the composite permittivity dielectric buried layer on the potential andelectric field distributions in the drift region are analyzed theoretically. Meanwhile, it isfound from the analysis of the potential well analytical model that the highconcentration holes are accumulated periodically on the composite permittivitydielectric buried layer in the off-state, and the mechanism of its formation is analyzedtheoretically. The results show that the potential and the electric field distributions in thedrift region obtained from the potential well analytical model are in good agreementwith the simulation results. In the off-state, the influences of the different permittivity inthe composite permittivity dielectric buried layer on the potential and electric fielddistributions in the drift region are analyzed by the proposed potential well analyticalmodel, and the analytical results are applied to the structure design of high voltage SOIdevice to improve the breakdown voltage and alleviate the self-heating effect.Second, based on the proposed potential well analytical model, a kind of novelhigh voltage SOI device with variable permittivity dielectric buried layer is proposed.The buried layer in this kind device is composed of the low permittivity dielectric withthe relative permittivity of2.65and the Si₃N₄dielectric. The vertical BV is enhanced bythe low permittivity buried layer, while the lateral BV is also enhanced by the electricfield peaks in the drift region introduced by the composite permittivity dielectric buriedlayer, resulting in a increased BV. Include:（1） high voltage SOI LDMOS withcomposite permittivity dielectric buried layer （CK SOI LDMOS）, which achieves theBV of213V with1μm SOI layer and1μm dielectric buried layer;（2） high voltage SOILDMOS with variable permittivity dielectric buried layer （CD SOI LDMOS）, in whichthe BV is increased from287V of the conventional SOI LDMOS to362V. In addition,the self-heating effect of this kind device is alleviated by the Si₃N₄dielectric in theburied layer at the same time. Furthermore, the low permittivity dielectric is studiedexperimentally, and a SiOCF film with the relative permittivity of3.1587is obtained.Third, based on the theoretical analysis, a kind of novel trench high voltageLDMOS structure with low Ron,spis proposed. The influences of the channel resistance,the optimized doping concentration of the drift region and the device length on the Ron,spare obtained from theoretical analysis. The theoretical analysis indicates that the Ron,spof trench high voltage LDMOS is reduced by shortening the device length, and then the Ron,spcan be further reduced by reducing the channel resistance or increasing theoptimized doping concentration of the drift region. Based on the theoretical analysis, thetrench high voltage SOI device with dual vertical field plate （DFPT MOSFET） isproposed. In addition to increasing the BV, the formation of the dual vertical field platein the dielectric trench also increases the optimized doping concentration of the driftregion due to the assisted depletion effect, which results in a reduced Ron,sp. The Ron,spof110mΩ·cm²is thus obtained for the DFPT MOSFET when the BV is589V. At thesame time, the trench high voltage SOI LDMOS with a embedded p-island （PT SOILDMOS） is also proposed, in which the Ron,spis further reduced because of the assisteddepletion effect of the embedded p-island. The results show that the Ron,spreduces to10.2mΩ·cm²for the PT SOI LDMOS with a BV of261V. In addition, the trench highvoltage device with dual gate （DG LDMOS） and the trench high voltage SOI devicewith a extended gate （EGT SOI MOSFET） are also studied, and the EGT SOI MOSFETis prepared experimentally. Simulation results show that the BV of226V and the Ron,spof5.9mΩ·cm²are obtained for the DG LDMOS, while the Ron,spof3.3mΩ·cm²isobtained for the EGT SOI MOSFET with the BV of233V.