Vertical Breakdown Theory And New Strucutres Of SOI Lateral High Voltage Device

SOI (Silicon On Insulator) fully exerts the potential of silicon-based integrated circuit due to the advantages such as superior isolation, reduced leakage current, high speed, perfect irradiation and low power dissipation because of its unique structure, and therefore, it is widely developed and applied. Dielectric buried layer prevents the depletion layer spreading into the substrate layer, and so, as the footstone of SOI HVIC (High Voltage Integrated Circuit), SOI lateral high voltage device limits the application of SOI HVIC because of its low vertical breakdown voltage (BV) as a result of the Gauss-theory without interface charges. Up to now, the breakdown voltage of the applied SOI device is less than 600V. To resolve the problem, semiconductor researchers have carried out plentiful work, and new theory models and new device structures are their two key disquisitive aspects.In this thesis, the novel theory, the new model and the novel device structures are researched aiming at the vertical breakdown voltage of SOI lateral high voltage devices. A unified vertical breakdown voltage of ENDIF (ENhanced DIelectric layer Field) theory is consummated. Based ENDIF, a new silicon critical electric field model based on threshold energy avalanche breakdown classical theory and two kinds of novel charge-mode high voltage devices (SOI high voltage devices with interface charge island and composite buried layer) are reported. Operating mechanisms of the proposed devices are investigated, the analytical models of breakdown voltage and electric field are presented, and some experimental results are obtained.1. ENDIF is consummated. Based on the concept of critical field approaching for dielectric buried layer, ENIDF is proposed whose standpoint is to increase vertical breakdown voltage by enhancing the electric field of dielectric buried layer (EI). From the continuity theorem of electric displacement including interface charge, three approaches to enhance dielectric layer electric field are presented by the ENDIF:①using a thin silicon layer with high critical electric field (ES,C);②introducing low permittivity dielectric buried layer;③implementing interface charges on the interface of dielectric layer. The ENDIF can well explain several existing SOI HV device structures and it is a new and effective rule for SOI HV devices, giving theoretical direction for increasing the vertical breakdown voltage.2. Based on the ENDIF, the analytical mode of silicon critical electric field on silicon layer thickness (tS) is firstly presented. By threshold energy avalanche breakdown classical theory and the effective ionization rate considering the threshold energy of silicon, a new dependence of ES,C on tS which is applicable for both thin and thick silicon layer and a new formula of ES,C on impurity concentration in silicon (Nd) which is applicable for both low and high impurity concentration are obtained, from which, expressions of EI and BV are given. Moreover, the semi-classical model of the relaxation dependence between critical electric field and ionization rate for nano-level unltrathin silicon layer is discussed. Finally, the researchful method is used to other semiconductor materials and devices.3. Based on the ENDIF, two kinds of novel charge-mode high voltage devices - interface charge island SOI and SOI with composite buried layer are reported.(1) Interface Charge Islands SOI device The structures are characterized by a charge islands layer on the interface of dielectric buried layer in which the equidistant high concentration n+-regions are inserted. Interface charges are located on the interface by the compositive operations of electric field force and Coulomb's force with high concentration ionized donors in the undepleted n+-regions. The induced inversion holes greatly enhance the electric field of the buried dielectric layer and therefore, effectively increase device breakdown voltage. Include:①CI SOI (Charge Islands SOI). BV=606V are obtained on 5μm silicon layer and 1μm dielectric buried layer, and EI reaches to 582V/μm;②Charge Islands partial-SOI (CI PSOI). An analytical model of the vertical interface electric field for the CI PSOI is derived. BV=631V is obtained on 5μm silicon layer, 1μm dielectric buried layer, 80μm drift region and 15μm silicon window, and enhanced EI (△EI) by interface charges reaches to 498.2V/μm, at the same time, the maximal surface temperature of CI SOI reduces by 7.66K and 14.91K in comparison with the conventional PSOI and SOI, respectively;③Improved Charge Islands partial-SOI (ICI PSOI). BV of 663V for ICI PSOI are obtained on 5μm silicon layer, 1μm dielectric buried layer, 80μm drift region and 20μm silicon window, which is larger by 85V than that of CI PSOI with the same structure parameters, with a low self-heating effect;④CI SOI based on ESIMOX. BV of 230V is obtained on 2μm silicon layer, 0.375μm dielectric buried layer and 15μm drift region, which is much larger than that of the conventional SOI;⑤DCI PSOI (Double-side Charge Islands SOI). BV=750V is obtained on 5μm silicon layer, 1μm dielectric buried layer and 70μm compared with 685V of CI SOI and 206V of the conventional SOI.(2) SOI with Composite Buried Layer (CBL SOI)The dielectric buried layer of the structures is made of two oxide layers and polysilicon between them. Its breakdown voltage is shared by the two oxide layers, furthermore, the charges on the bottom interface of polysilicon layer enhance the second buried layer electric field, thus breakdown voltage is increased. Include:①SOI with Single-Window Composite Buried Layer (SWCBL SOI). There is a single silicon window in the first buried layer. BV=865V is obtained on 20μm silicon layer, 2.5μm the first buried layer, 0.5μm the second buried layer and 80μm compared with 633V of the conventional SOI.②SOI with Dingle-Window Composite Buried Layer (DWCBL SOI). There are two silicon windows in the first buried layer, and two buried layers are connected by an oxide layer. A high BV of 1040V is obtained on 20μm silicon layer, 2μm the first buried layer, 1μm the second buried layer and 80μm, and△EI reaches to 498.2V/μm, with a low self-heating effect. Moreover, 761V SWCBL SOI LDMOS is experimentally obtained on 20μm silicon layer, 2.5μm the first buried layer, 0.5μm the second buried layer and 80μm, which breaks through the BV <600V limitation of the conventionally applied SOI device.