High-Speed Wireless Communication System Design And Key Technology Research

Because of the increasing demand for real-time multimedia service and high throughput data service, as well as the rapid development of Internet technology, there is a big stage for the flourish of wireless communication system. Furthermore, the future wireless communication technology will strive for higher throughput, higher spectrum utilization and more diverse and personalized services. Therefore, it is necessary to do further research of the high-speed wireless communication system.The tasks of this thesis are mainly based on the National Science and Technology Major Project "Research and verification of key technology for the High-Speed Wireless LAN System". This project targets to study the Wirless Local Area Network (WLAN) wireless interface technology, to design and implement a demonstration system with Field programmable Gate Array (FPGA) hardware and to verify the key technology on the system. The author is responsible for the design of system parameter, system hardware and software scheme of the high-speed WLAN communication system. Besides, the study and implementation of some key technologies of the system are also dicussed in this thesis.First, in this thesis, the high-speed wireless communication system is researched. Due to the scene of still and slow moving aiming at the indoor environment, and the aim of more than Gbps throughput and 15 bit/s/Hz in spectrum utilization, the in-depth analysis is deployed in system level. System design is not confined to the parameters aspect, including Physical Layer (PHY) link structure, system parameter and frame structure. What’s more, the system software protocol level, which means the Media Access Control (MAC) layer framework and implementation structure, and the system hardware architecture level are also concerned.Second, in this thesis, the development, expression and classification methods of the Low Density Parity Check Code (LDPC) are discussed. Besides, this thesis also emphatically analyzes the structured LDPC coding algorithm, which is suitable for the hardware implementation, and derives the LDPC decoding algorithm from Belief Propagation (BP) algorithm to Log-Likelihood Ratio BP (LLR_BP) algorithm and Uniformly Most Powerful (UMP) BP-Based algorithm. Furthermore, the triple semi-parallel LDPC decoding architecture is put forward, which is based on the UMP BP-Based algorithm for its less complexity in hardware implementation. The triple semi-parallel architecture represents in three aspects, including paralleling the initial process with iterative decoding process, two-decoding simultaneously and using two computing units for one block. This method maximizes the rate of LDPC decoder, and guarantees the reliability of the high-speed communication system. Finally, this thesis analyzes the MAC-PHY interface, which is responsible for transparent transmission between media access control layer and physical layer. The operating process is designed for the Access Point (AP) and Mobile Terminal (MT). What’s more, the communication scheme with PCIe bus, DDR3 memory and high-speed interface module between FPGAs is concerned.