The Design Of PCI Express Transmission Based On FPGA

As the third generation IO bus technology, PCI Express(PCIE) has a lot advantagesuch as high transmission bandwidth, new interconnect architecture, highly compliablefor PCI bus,etc and so been widely used in computer platform. In order to give full playto the advantages of PCIE bus, promote PCIE bus to be applied in embedded system,this article designes a PCIE data transmission system based on FPGA, provides a newlow cost solution for PCIE data transmission.This article employs the idea of top-down design to conduct the top-level design ofPCIE data transmission system and module division on the basis of in-depth studiesabout the PCIE protocol specification. Finally this study completes the RTL description,simulation and verification of PCIE data transmission system application layer, carriesout the analysis of the simulation results and tests the system practically. This articleincludes the following aspects:First of all, this article carries out in-depth studies about the PCIE protocol,alalyses the condition of PCIE native endpoint device implmention, selects thedevelopment platform, and then conducts the top-level design of PCIE datatransmission system and module division on the basis of in-depth understanding ofPCIE protocol.Secondly, this study configures the PCIE IP in Quartus II integrate developmentenvironment and introduces the interface of PCIE IP, and then employs Verilog HDL toRTL design of PCIE IP configuration module, support module of application layer, coremodule of application layer. The PCIE IP realizes function of PCIE protocol whichcommunicates with application layer through64bit Avalon-ST interface. PCIE IPconfiguration module realizes the sampling of PCIE IP configuration signals andconfiguration of PCIE error report capability register in configuration space throughLMI interface. The support module of application layer realizes receiving andtransmitting interface transformation, receiving interface buffer and MSI buffer. Thecore module of application layer realizes the data transmission function in Rc_slave andchaining DMA way. This article realizes the chaining DMA data transmission functionon the basis of DMA, reduces consumpustion of CPU resourcse, greattingly improvesthe efficiency of data transmission.Finally, it draws up simulation and tests for PCIE data transmission system. This article builds the testbench of system, which is used for function simulation of wholesystem. Compiles the whole design and uses the circuit been generated to configures theFPGA to verify the design time sequence. Run the test program on PC to test the systemin practical. Analyze the result of simulation and test.Through the thorough analysis of the simulation and test results of PCIE datatransmission system, it’s indicated that each module of IP core logic functions meetsrequirements of the design. System can exchange data with PC main memory inRc_slave and chaining DMA way, the DMA read speed archeives173MB/S and theDMA write speed archeives207MB/S.This design provides feasible and effectiveimplementations for PCIE data transmission using low cost FPGA, promotes the PCIEbus range of application and has good prospects.