Implementation Of PCI Express Interface Based On Altera FPGA

PCI Express(PCI-E)is a high performance interconnect protocol, because of itshigh bandwidth, high compatibility with the PCl bus, and communication withdifferential serial point to point, it is widely used in many areas, such as the networkadapter, graphics accelerator, servers, large data transmission and embedded systems,etc. The Altera provides the solutions which is compatible with PCI-E1.0and PCI-E2.0, uses GX transceiver technology, and possesses superior jitter performance andsignal integrity. Built-in PCI-E hard IP contains all functions which processing layer,data link layer and physical layer require and the vast majority of optional features.This thesis first introduces the background, technology advantages and prospectsof PCI-E protocol, and some base studies about the architecture, transaction type,transaction routing, configuration space, the interrupt service etc. Then it makes somebrief introduction on the hardware platform of PCI-E interface, PCB laminated structureand the advantage in achieving PCI-E interfaces of the EP4CGX50CF23I7. And moreimportantly it focus on the routing specifications and routing strategy of DDR2SDRAM and PCI-E and stresses the importance of impedance matching andelectromagnetic compatibility. Finally, based on studies of core structure of PCI-E hardIP, it gives out the design scheme of configuration space management module, datareception and transmission module, MSI interrupt content service module, chain DMAmodule that are parts of achieving PCI-E endpoint devicesAs the FPGA has high flexibility and integration, in design of the system thespecified PCI-E is replaced by the FPGA with PCI-E hard core, not only simplifyingcircuit design and reducing system cost and power consumption, but also improving thestability and flexibility of the system.