Integration And Verification Of PCIe Interface In FPGA Chip

Peripheral Component Interconnection Express(PCIe)is an important configuration in the mainstream Field-Programmable Gate Array(FPGA)as a data high-speed transmission interface.However,due to the late start of domestic FPGA manufacturers,the products are mainly concentrated in the low-end market without PCIe interface.The research on PCIe integration technology in FPGA has less accumulation.Therefore,in the independent research and development process of FPGA,the research about this technology has important engineering application value and significance.This paper carries out secondary development of PCIe IP core,completes the integration and verification of PCIe interface in FPGA chip,and finally realizes the addition of PCIe interface function in FPGA.Because of the complex interface and large number of modules of PCIe IP core,it is difficult for the user to use the PCIe IP core directly.At the same time,the configuration is single and not changed after generatation,so the flexibility is extremely poor.This paper addresses the difficulty of enabling IP cores for ASICs to be suitable in flexiblely configurable FPGAs.The optional functions such as interrupt and Base Address Register are redesigned.The software can quickly set the PCIe interface which greatly increases the flexibility of the interface by adding configurable interface signals.At the same time,it simplifies configuration and reduces power consumption by turning off the unnecessary initial interface of IP cores.Then in order to facilitate the user's operation,the IP core is encapsulated in the outer layer,and is connected to the user logic through an interface of the Advanced eXtensible Interface Stream,which is familiar to most users.In the verification,the PCIe verification platform based on Universal Verification Methodology is built and optimized.Various inspection mechanisms are adopted and Direct Memory Access comparison mechanism is added which improve the comprehensiveness and accuracy of verification.The design is verified by an improved verification platform.The verification function points are extracted according to the protocol and the verification cases are designed to verify whether the various functions of PCIe in different modes can be realized.In the end,the functional coverage defined by this design reaches 100%,and the code coverage rate is over 90%.It supports x1,x2,and x4 configurations,and the speed can reach 5GT/s.The design is synthetized with the TSMC 28 nm LP process.The static power of optimized design is reduced by 10.5% at 25°C,8.7% at 85°C,and the area of optimized design is reduced by 6.3%.It is expected to tapeout in TSMC 28 nm LP process in June 2019.