Research On PCIE Module In Ten Million Gate FPGA

The bus is a communication network for the information exchange of various functional components in the communication system and one of the key technologies of high-performance communication devices.In high-speed data processing systems,the system bus always becomes the bottleneck which limits the system performance.PCI Express bus technology is the third-generation system bus technology and the mainstream IO bus supported by current high-speed devices.PCI Express bus technology adopts serial differential signal transmission mode and end-to-end transmission architecture,and it has performance advantages such as high frequency,high bandwidth and low power consumption.Integrating the PCI Express bus interface in a high-performance chip can effectively improve the system performance of the chip in a high-speed data transmission environment.Research in this field has important engineering significance.Based on a project of FPGA chip design with tens of millions of gates,this paper studies the technical route of PCIE module integration in high-performance FPGA devices.The chip designed in this article is a self-developed domestically leading high-performance FPGA device with tens of millions of gates using the industry's advanced 28nm process.The amount of integrated transistors reaches hundreds of millions,and the chip contains 693,120 programmable units and three PCIE IP cores.Each PCIE core supports PCI Express 3.0 specification which supports up to 8transmission channels with a single channel transmission rate of 8GT/s max.The FPGA chip design in this article uses the classic GRM structure,which simplifies the integration of the PCIE IP core.Based on the link constraint relationship provided by the software,the author links the input and output ports of the functional modules around the PCIE IP core with the corresponding interconnection resource ports in the FPGA on the top layer of the FPGA chip,and realizes the PCIE IP integration on the circuit netlist file.The author builds a verification platform based on gray-box verification using Verilog.The reusable PCI Express protocol verification vector instruction set is encapsulated in the platform through TASK function.Through behavior modeling of PCIE IP,fast simulation verification is realized in VCS software.The entire verification environment adopts an end-to-end circuit simulation model,and relevant transaction stimulus are sent through upstream devices,then downstream devices receive stimulus data packs and generate responses.Once the simulation is completed,the function result can be analyzed by calling key internal signals and signals from the external input and output ports of the IP core.After the chip is taped out,the author completes the application test of the taped FPGA using the FPGA chip application test platform.The application test project realizes the calling of the PCI Express interface of the FPGA chip and its supporting CMT,SERDES,CLB,SRAM and other modules.Then real-time signal transmission quality eye diagrams and bit error rate analysis diagrams are obtained by a bandwidth oscilloscope.After that the reliability of the PCI Express interface in the FPGA chip is verified through actual tests.This article successfully completes the integration and verification of the PCIE module in the FPGA chip as well as the application test after the tape-out.A verification platform is built to support the verification work,and the functional coverage of the final verification reaches 100%.In the test process of the PCIE interface of the FPGA chip after the tape-out,the eye widths and eye heights of the transmission quality eye diagram are 125ps and 400m V in 8GT/s mode,200ps and 400m V in 5GT/s mode together with 400ps and 400m V in 2.5GT/s mode.The eye width under 10^-12 bit error rate is greater than 0.6 UI.Statistics above prove that the signal transmission quality of the PCIE interface of the FPGA chip in the three modes meets the design requirements.