Design Of RAM Management And Control System In1553B Data Bus Interface Circuit

MIL-STD-1553B is a centralized control and Time Division Command/Response Multiplex Data Bus military standard, it has been widely applied in avionics systems because of its advantages of good topology, high speed and high reliability. It also made great contributions to the development of integrated avionics system. The key of1553B bus system is bus interface circuit, but, at present domestic design and production technology of1553B bus interface circuit is not mature enough, and most of them are imported from foreign companies. So the independent research of1553B bus interface circuit is of great significance and value for china.1553B bus interface circuit mainly consists of transceivers, Manchester encoding and decoding,1553B protocol processor and shared memory. It can complete all functions in BC, RT and MT mode. Shared memory stores all data transmitted between the terminal subsystem and the data bus, these data are based on certain message format for transmission. In different mode, the shared memory message processing is different, so the shared memory storage and management mechanism is different, and the memory read and write logic is also different. With the expanding of1553B bus application filed,1Mbps data transfer rate does not meet the needs of all users, so1553B bus interface design is also developing to high-speed. Based on the detailed studying of the MIL-STD-1553B data bus protocol and the foreign chip design, combined with emerging EDA technologies, carried out a detailed design of shared memory control logic in protocol processor, it can achieve data storage and transmission management in BC and RT mode, and also can improve the throughput of the shared memory to meet the development needs of the high-speed bus interface circuit.According to the specific functions of the new1553B interface circuit defined, this paper apply top-down designing method to put forward the total design scheme, and then put forward Pin Description of each module, the state machine transition diagram as well as so(?) simulation results of the module. This design use VerilogHDL to descript, and then (?) specialized synthesize software to synthesize and optimize. According to the function simulation verify that the design be able to complete data storage and transmission management in BC mode, and data transmission of single massage mode, double buffer mode and circluler mode in RT mode.