The Design And Application Of Reusable Interface IP Core

With the development of SoC design technology, IP core is becoming themain trend of the SoC design, which is a powerful security for SoC products to seizethe market. However, the current IP core development can not keep up with thedemand of the market. One of the reasons is that fewer high-quality reusable IPcores are available. According to the market survey by CSIP against IP core, itshows that interface IP core is one of the most wanted IP cores. Therefore, wecarried out the study of high-performance and reusable interface IP core design.In this dissertation, based on the study of the method to reusable IP coredesign, we designed a high-performance reusable interface IP core——UART. Inthe reusable implementation of UART design, we used the method to theparameters design of IP core, adopted the Standard Verilog RTL code for encoding, used the synchronous design and the elimination of the metastable method toincrease reliability, and followed reusable interface design standards such asusingthe Wishbone bus interface design for easy integrating into a SoC.In the UART functional design, the main contributions are: abandoning thetraditional small-capacity synchronous FIFO buffer module256bytes large-capacity asynchronous FIFO design to improve transfer rates; designing an adaptivebaud rate generator, without the division factor setting in advance to get baud rateclock so that the area increase of PLL-consumption issues is avoided, proposing anauto-tuning baud rate generator to produce the desired baud rate adaptive clock.Based on the UART for a power analysis, we propose a power management model,successful design of a power management module, effectively reducing theunnecessary power consumption.Finally, according to the design process of the IP core, after completing thedesign of all modules of UART, it’s carried on a verification, synthesis andoptimization. A script on area and cycle time to control document with the TCL language is written and carried on logic synthesize with the DC. Verificationprocess is followed with ModelSim to carry out function verification, VCS for Gate-level simulation, Formality for equivalent validation, PrimeTime for cycle timeverification.