Soc-based Reusable Ip Core Design Method

The development of Semiconductor Technology and EDA tools helps make SoC (System on Chip) a reality. The size and complexity involved in designing SoC is continuously out-pacing the designer productivity. Prevailing IP(intellectual property)Reuse methodologies for system integration are essential to achieving the engineering quality of today's large, complex ICs. Firstly, the design of reusable soft-IP must follow the standard flow and specification of IP design; Then the RTL level circuit models using HDL are built; Thirdly, EDA tools synthesize the RTL models, and simulate them by software simulation, for testing and verifying the designed soft-IP by the functional and timing restrains; Lastly, the designed soft-IP cores must have been fitted to FPGA for testing them, and the function of the designed soft-IP has been completely verified.This paper outlines the issues of soft-IP methodologies, thinking in system level design style. Then the standard soft-IP design techniques have been presented in detail. A full description of VHDL coding style for EDA Synthesis tool of Actel FPGA has been introduced in the paper. For the test and verification of soft-IP, the paper presents a solution of Design For Test technique, of which the BIST(Built-in Self Test) is described in particular. Based on a thorough study of Soft-IP design methodologies, two sort of widely-used Manchester encoder and decoder Soft-IP cores have been designed, in need of developing subsequence instruments.The paper also highlights the design and implementation of "Testing Panel for Digital Acoustic Well Logging Device" platform, which integrates the designed Manchester encoder and decoder Soft-IP cores. The platform also verifies the Soft-IP cores, and makes itself be the combination of verifying and using Soft-IP cores, and produces satisfying results. The paper introduces the "Induce Array Well Logging Device" to prove the reusability of Soft-IP cores lastly.