Design Of UART And DMA Controller Soft IP Core With Application To SOC

With the development of the Super Large-Scale Integrate Circuit and the deep sub-micron fabricate technology, design using SOC ( System-on-a-Chip ) methodology is becoming the trend of the Integrate Circuit Industry. As the base of SOC design, IP(Intellectual Property) core plays an important part, not only in the SOC industry, but also in the total Integrate Circuit Industry.UART (Universal Asynchronous Receiver/Transmitter) and DMAC (Direct Memory Access Controller) are the important components of the Input/Output system. Besides, they are both in very common use in the SOC system. Under the background that we are dropped in the IP Core industry, and our cores are poor in both quantity and quality, this paper focused on the research work of the Reusable Design Methodology, and achieved in the designing of UART and DMAC IP Core. The work not only provided the practice experience of IP Core design, but also enriched the IP Core library of our country.First, the general introduce of the Input/Output system is given in the paper, which is the basis of the design and implementation. Further, the design idea and design details of each module in the UART design and DMAC design are described. The APB bus is used in the UART design, with a digital filter and the function of auto baud rate detect included. In the DMA controller, AHB bus is used, and multi-trigger-mode and multi-transfer-mode are included, which make data transfer between peripheral and peripheral, memory and memory, or peripheral and memory possible.Finally, the verification plan and the result are presented in this paper. The entire verification is divided into two departments: the logic verification and the performance verification after synthesis. In the logic verification period, fully verification is given both in the single module level and system level. Besides, FPGA verification is given to UART, to test the compatibility of the UART serial interface. After the logic verification, logic synthesis, formality verification, static time analysis and scan chain inserting are given, using the EDA tools of SYNOPSYS, to ensure that the design is strictly submit to the reuse-design specification.The result of the verification indicates that the UART and DAMC IP cores are suitable for what is expected and can be used into other SOC applications as a single module. The achievements of this paper have important practical and realistic significance to IP core design and implementation in SOC field.